Hitachi H8S/2646 Hardware Manual

Text of Hitachi H8S/2646 User Guide:

• Hitachi H8S/2646, 455 Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit

• Hitachi H8S/2646, 206 Read Write Read Write Address ø DTC activation request DTC request Data transfer Data transfer Transfer  information write  Transfer  information write  Transfer information read Transfer information read Vector read Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status. Table 8-8 DTC Execution Statuses Mode Vector Read I Register Information Read/Wri

• 11 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 28 A6 A6 PC6/A6/SEG7 PC6/SEG7 29 A7 A7 PC7/A7/SEG8 PC7/SEG8 30 PB0/A8/SEG9 PB0/A8/SEG9 PB0/A8/SEG9 PB0/SEG9 31 PB1/A9/SEG10 PB1/A9/SEG10 PB1/A9/SEG10 PB1/SEG10 32 PB2/A10/SEG11 PB2/A10/SEG11 PB2/A10/SEG11 PB2/SEG11 33 PB3/A11/SEG12 PB3/A11/SEG12 PB3/A11/SEG12 PB3/SEG12 34 PB4/A12/SEG13 PB4/A12/SEG13 PB4/A12/SEG13 PB4/SEG13 35 PB

• Hitachi H8S/2646, 753 Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23-1 lists the absolute maximum ratings. Table 23-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage V CC PMWV CC –0.3 to +7.0 V LPV CC Input voltage (OSC1, OSC2) V in –0.3 +3.5 V lnput voltage (XTAL, EXTAL) V in –0.3 to A CC +0.3 V Input voltage (ports 4 and 9) V in –0.3 to AV CC +0.3 V Input voltage (ports A, B, C, D, E, ports PF2, PF4 to PF6) V in –0.3 to LPV CC +0.3 V Input voltage (ports H and J) V in –0.3 to PWMV CC +0.3 V Input voltage (except ports 4, 9, A, B, C, D, E, ports PF2, PF4 to PF6, H

• Hitachi H8S/2646, 380 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. Compare match signal  Write signal  Address  ø Buffer register address  Buffer register  TGR write cycle  T1 T2 N TGR N M Buffer register write data Figure 10-52 Contention between Buffer Register Write and Compare Match

• Hitachi H8S/2646, 1102 R PF2DDR C QD Reset Internal data bus WDDRF Reset WDRF R PF2DR C QD PF2 RDRF RPORF Wait input Bus controller Wait enable Mode 4/5/6 Mode 4/5/6 WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (b) Port F Block Diagram (Pin PF2)

• Hitachi H8S/2646, 714 Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) *3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)  φ V CC FWE t OSC1 Min 0µs t MDS t MDS *2 t MDS t RESW MD2 to MD0 RES SWE bit Mode change *1 User mode Boot mode User program mode SWE set SWE  cleared  Programming/ erasing possible Wait time: x Wait time: 100 µs Programming/ erasing possible Wait time: x Wait time: 100 µs Programming/ erasing p

• 878 MCR—Master Control Register H'F800 HCAN HCAN Sleep Mode 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled Message Transmission Method 0 Transmission order determined by message  identifier priority 1 0 1 Transmission order determined by mailbox  (buffer) number priority (TXPR1 > TXPR15) Halt Request HCAN normal operating mode HCAN halt mode transiti

• Hitachi H8S/2646, 250 9.6.2 Register Configuration Table 9-9 shows the port 5 register configuration. Table 9-9 Port 5 Register Configuration Name Abbreviation R/W Initial Value *2 Address *1 Port 5 data direction register P5DDR W H'0 H'FE34 Port 5 data register P5DR R/W H'0 H'FF04 Port 5 register PORT5 R H'0 H'FFB4 Notes: *1 Lower 16 bits of the address. *2 Value of bits 2 to 0. Port 5 Data Direction Register (P5DDR) Bit:76543210 — — — — — P52DDR P51DDR P50DDR Initial value : Undefined Undefined Undefined Undefined Undefined 000 R/W:————— WW W P5DDR is an 8-bit write-only register that specifies whether individual bits are

• Hitachi H8S/2646, 112 Origin of Vector Address *1 Interrupt Source Interrupt Source Vector Number Advanced Mode IPR Priority TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TPU channel 1 40 41 42 43 H'00A0 H'00A4 H'00A8 H'00AC IPRF2 to 0 High TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TPU channel 2 44 45 46 47 H'00B0 H'00B4 H'00B8 H'00BC IPRG6 to 4 TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (

• Hitachi H8S/2646, 737 22.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit:76543210 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : 0 0 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRB (H8S/2646, H8S/2646R, H8S/2645) Bit:76543210 MSTPB7 MSTPB6 — MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W — R/W R/W R/W R/W R/W MSTPCRB (H8S/2648, H8S/2648R, H8S/2647) Bit:76543210 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRC Bit:76543210 MSTPC7 — MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : 1 1 1 1 1 1 1 1 R/

• 1002 IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K

• Hitachi H8S/2646, 390 11.1.4 Registers Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name Abbreviation R/W Initial Value Address *1 PPG output control register PCR R/W H'FF H'FE26 PPG output mode register PMR R/W H'F0 H'FE27 Next data enable register H NDERH R/W H'00 H'FE28 Next data enable register L *4 NDERL R/W H'00 H'FE29 Output data register H PODRH R/(W) *2 H'00 H'FE2A Output data register L PODRL R/(W) *2 H'00 H'FE2B Next data register H NDRH R/W H

• 29 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have bee

• Hitachi H8S/2646, 37 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are f

• Hitachi H8S/2646, 545 15.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). When receiving a remote frame, the corresponding remote-request register (REPR) is also set at the same time. RXPR Bit: 15 14 13 12 11 10 9 8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit: 7 6 5 4 3 2 1 0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(

• Hitachi H8S/2646, 246 Pin Selection Method and Pin Functions P33/TxD1 Switches as follows according to combinations of bit TE of SCR1 and bit P33DDR. TE 0 1 P33DDR 0 1 — Pin function P33 input pin P33 output pin* TxD1 output pin* Note: * When P33ODR = 1, it becomes NMOS open drain output. P32/SCK0/ IRQ4 Switches as follows according to combinations of bit C/A of SMR0, bits CKE0 and CKE1 of SCR0, and bit P32DDR. CKE1 0 1 C/A 01— CKE0 0 1 — — P32DDR 0 1 — — — Pin function P32 input pin P32 output pin SCK0 output pin* SCK0 output pin* SCK0 input pin IRQ4 input Note: * When P32ODR = 1, it bec

• Hitachi H8S/2646, 96 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), PC break controller (PBC), A/D converter, Hitachi controller a

• 573 When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXP

• Hitachi H8S/2646, 944 MD81—Message Data 81 H'F8F0 HCAN MD82—Message Data 82 H'F8F1 HCAN MD83—Message Data 83 H'F8F2 HCAN MD84—Message Data 84 H'F8F3 HCAN MD85—Message Data 85 H'F8F4 HCAN MD86—Message Data 86 H'F8F5 HCAN MD87—Message Data 87 H'F8F6 HCAN MD88—Message Data 88 H'F8F7 HCAN MD81 MD82 MD83 MD84 MD85 MD86 MD87 MD88 MSG_DATA_1 (8 bits) MSG_DATA_2 (8 bits) MSG_DATA_3 (8 bits) MSG_DATA_4 (8 bits) MSG_DATA_5 (8 bits) MSG_DATA_6 (8 bits) MSG_DATA_7 (8 bits) MSG_DATA_8 (8 bits) MD91—Mes

• 321 Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 3 0000TGR3A is Output disabled (Initial value) 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 10 output 1 output at compare match 1

• Hitachi H8S/2646, 676 Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period ( 1 or more bits ) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustm

• Hitachi H8S/2646, 620 17.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — OTS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 Read/Write — — — — — — — — — — — — — — — — There are four PWDTR1x registers (PWDTR1A, 1C, 1E, 1G). PWDTR1A is used for outputs PWM1A and PWM1B, PWDTR1C for outputs PWM1C and PWM1D, PWDTR1E for outputs PWM1E and PWM1F, and PWDTR1G for outputs PWM1G and PWM1H. PWDTR1

• Hitachi H8S/2646, 1081 C.2 Port 2 Block Diagrams R P2nDDR C QD Reset WDDR2 Reset WDR2 R P2nDR C QD P2n RDR2 RPOR2 TPU module Output compare output / PWM output enable Output compare output / PWM output Input capture input * Internal data bus Legend WDDR2 WDR2 RDR2 RPOR2 n = 0 to 3, 5, and 7 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C-2 (a) Port 2 Block Diagram (Pins P20 to P23, P25, and P27)

• Hitachi H8S/2646, 754 23.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 23-1. 3 3.5 4 4.5 5 5.5 6 24 20 16 12 8 4 0 Operating range in high-speed, medium-speed, and sleep modes Frequency (MHz) Power supply voltage (V) 3 3.5 4 4.5 5 5.5 6  32.768     0 Operating range in watch, sub-active, and sub-sleep modes  Frequency (MHz) Power supply voltage (V) Figure 23-1 Power Supply Voltage and Operating Ranges

• Hitachi H8S/2646, 462 Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 13-10 Serial Transfer Formats (Asynchronous Mode) PE 0 0 1 1 0 0 1 1 — — — — S 8-bit data  STOP S 7-bit data  STOP S 8-bit data  STOP STOP S 8-bit data  P STOP S 7-bit data  STOP P S 8-bit data  MPB STOP S 8-bit data  MPB STOP STOP S 7-bit data  STOPMPB S 7-bit data  STOPMPB STOP S 7-bit data  STOPSTOP CHR 0 0 0 0 1 1 1 1 0�

• Hitachi H8S/2646, Section Page Description 23.1 Absolute Maximum Ratings Table 23-1 Absolute Maximum Ratings 753 Input voltage (OSC1, OSC2) V in –0.3 +3.5 V lnput voltage (XTAL, EXTAL) V in –0.3 to A CC +0.3 V Input voltage (ports 4 and 9) V in –0.3 to AV CC +0.3 V Input voltage (ports A, B, C, D, E, ports PF2, PF4 to PF6) V in –0.3 to LPV CC +0.3 V Input voltage (ports H and J) V in –0.3 to PWMV CC +0.3 V Input voltage (except ports 4, 9, A, B, C, D, E, ports PF2, PF4 to PF6, H and J) V in –0.3 to V CC +0.3 V 23.3 DC Characteristics Table 23-2 DC Characteristics 755, 758 Input high voltage RES, STBY, NMI, FWE, MD2 to MD0 V IH V CC – 0.7 — V CC + 0.3 V EXTAL

• Hitachi H8S/2646, 591 16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) 15 AD9 0 R Bit   Initial value R/W :  : : 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11 AD5 0 R 10 AD4 0 R 9 AD3 0 R 8 AD2 0 R 7 AD1 0 R 6 AD0 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for th

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