Hyundai H-HT5115-N Service Manual

Text of Hyundai H-HT5115-N User Guide:

• Hyundai H-HT5115-N, ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 14/46 DEVICE OPERATIONS (Continued) AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy t RAS (min) and “tRP” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 23 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 Figure 20. Enter OTP Mode Power-up Timing Figure 21. Power-up Timing Table 8. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. Max. Unit t VSL (1) V CC (min) to CS# low 10 µs t PUW (1) Time delay to Write instruction 1 10 ms VWI (1) Write Inhibit Voltage 1 2 .5 V Note: 1.The parameters are characterized only. 2. VCC (max.) is 3.6

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 18 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 Figure 13 Block Erase Instruction Sequence Diagram Chip Erase (CE) (C7h/60h) The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instr

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 3 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 Figure.1 CONNECTION DIAGRAMS Figure 2. BLOCK DIAGRAM 8 - LEAD SOP / DIP 8 - CONTACT VDFN

• Hyundai H-HT5115-N, 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ASPDIF OP_Vref DV33 AVCC ARS ALF A_MUTE A_MUTE CENT OP_Vref AL AR LSCH SUB AR AL AKIN1 OP_Vref ARF OP_Vref ALS ASPDIF RCH LCH +12V +12V +12V +12V +12V +12V +12V ARS ALS ARF ALF +P12V OP_Vref A_MUTE A_MUTE A_MUTE RSCH A_MUTE OP_Vref AUDIO_MUTE OP_Vref A_MUTE AKIN2 AKIN1 AKIN2 COAXIAL OPTICAL +12V RSCH LSCH SUB CENT LCH RCH LCH RCH AUDIO_MUTE +P12V +P12V OP_Vref +12V DV33 +P12V AVCC ASPDIF [2] DV33 [1,2,3,6] AVCC [1,2,5,6] AL [2] AR [2] ARS [2] ALS [2] ARF [2] ALF [2] RCH [5] LCH [5] +P12V [1] AUDIO_MUTE [2] AKIN1 [2] AKIN2 [2] Title Size Document Number Rev Date: Sheet of MediaTek (ShenZhen) Inc. Drawn: Chec

• Hyundai H-HT5115-N, ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 8/46 AC CHARACTERISTICS (AC operating condition unless otherwise noted) -5 -6 -7 PARAMATER SYMBOL MIN MAX MIN MAX MIN MAX UNIT NOTE CAS latency = 3 5 6 7 CLK cycle time CAS latency = 2 tCC 10 1000 10 1000 10 1000 ns 1 CAS latency = 3 4.5 5.5 6 CLK to valid output delay CAS latency = 2 t SAC 6 6 6 ns 1,2 CAS latency = 3 2.0 2.5 2.5 Output data

• Hyundai H-HT5115-N, ABSOLUTE MAXIMUM RATINGS Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Note : 1.All voltages are referenced to V SS = 0V 2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V 3.V IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration 4.V IL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration AC OPERATING CONDITION (TA=0 to 70°C, V DD =3.3 ± 0.3V Note2 , V SS =0V) Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (5

• Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE 22 9-3 Built-in Audio-ADC Characteristics Test Condition: DSP MIC1 Gain = 0 (0) MIC threshold=0 DSP MIC2 Gain = 0dB.(2000) Apwin output Z= 600 Echo level = 0 dB Measure SPDIF output. CIC filter right shift 3 bit Test signal : 1K Hz sin wave Vpp(V) Max Input (wit

• Hyundai H-HT5115-N, ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 36/46 Read & Write Cycle at Different Bank @ Burst Length = 4 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP CL =2 CL =3 Row Active (A-Bank) Read (B-Bank) :Don't Care QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3 DDb0 QAa0 RAa CBc RAa CAa QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3 DDb0 QAa0 Write (D-Bank) HIGH RDb CDb RBc RBb RAc QBc0 QBc1 QBc2 QBc0 QBc1 Read (A-Bank) Row Active (D-Bank) Precharge (A-Bank) Row Active (B-Bank) t CDL *Note1 1921

• Hyundai H-HT5115-N, Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE 27 Input Instruction Hold After PSEN high T8 0 ns Input Instruction Float After PSEN high T6 1.0Tf-5 ns Port 0 Address to Valid Instruction T10 3.0Tf-20 ns Port 2 Address to Valid Instruction T11 3.5Tf-20 ns PSEN Low to Address Float T7 0 ns ADR[7:0] Inst. ADR[7:0] ADR[15:8] t0 t1 t2 t3 t4 t5 t7 t9 t6 t8 t10 t11 ALE PSEN Port 0 Port 2 Program Memory Read Cycle Timing Diagram 9-9 Digital Video Output Interface Parameter Symbol

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 32 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 ORDERING INFORMATION EN25F16 - 100 H I P PACKAGING CONTENT (Blank) = Conventional P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40°C to +85°C) PACKAGE H = 8-pin 200mil SOP W = 8-pin VDFN

• ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 44/46 PACKING DIMENSIONS 54-LEAD TSOP(II) SDRAM (400mil) (1:3) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.20 0.047 A1 0.05 0.10 0

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 2 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • 16 Mbit Serial Flash - 16 M-bit/2048 K-byte/8192 pages - 256 bytes per programmable page • High performa

• Hyundai H-HT5115-N, 5 5 4 4 3 3 2 2 1 1 D D C C B B A A TRINGPIO2 USB_DP LD-CD LD-DVD ASPDIF SP-A SL+ SL- LIMIT SP+ V20 F- F+ T+ T- C D IOA A B F AUDIO_MUTE DCLK MA[0..11] SF_DI DQ[0..15] SF_CS BA[0..1] RAS# SF_CK SF_DO DQM[0..1] CAS# WE# MDI1 V1P4 STBY TROPEN TROUT TRIN V_B V_R V_G CVBS_OUT F- T+ SP+ SP- SL- SL+ F+ FOO TRO DMO FMO FOSO DMSO FMSO TRSO ARF AL ALS AR ARS ALF GPIO3 STBY TROPENIOAGPIO4 LIMIT TROUTGPI36 TRCLOSE T- RFO V1P4 OPO OP- LDO2 TxD RxD GPIO7 GPIO8 GPIO9 AKIN1 VSCKUP1_6 VSDAUP1_7 DMSO FMSO TRSO FOSO SP-A SP- VSTBGPIO13 AVCC1 V20 USB_DM E AADVDD AVCC1 GPIO6 RFV33 89J_3V3 1V2 AVCC DV33 URST# TRCLOSEGPO5 VSTB RFO XI GPO_A GPO_BVR_DVD GPIO11 RFV12-2 GPIO6 SCART1GPIO10 HSYNC SCART2 VSYNCGP

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 6 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 239 0EF000h 0EFFFFh …. …. …. 14 224 0E0000h 0E0FFFh 223 0DF000h 0DFFFFh …. …. …. 13 208 0D0000h 0D0FFFh 207 0CF000h 0CFFFFh …. …. …. 12 192 0C0000h 0C0FFFh 191 0BF000h 0BFFFFh …. …. …. 11 176 0B0000h 0B0FFFh 175 0AF000h 0AFFFFh …. …. …. 1

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 16 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 Page Program (PP) (02h) The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page

• Hyundai H-HT5115-N, ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 11/46 BURST SEQUENCE (BURST LENGTH = 4) Initial Adrress A1 A0 Sequential Interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial A2 A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7

• Version 1.0 Specifications are subject to change without notice MT1389 J Desktop DVD Player SO C General Datashee t MEDIATEK CONFIDENTIAL, NO DISCLOSURE Revision History Revised date Contents of revision Reason for revision Page Remarks 2009 6 18 1 st Release Ver 1.0 Mediatek Confidential Only For SAC

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 24 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 Table 9. DC Characteristics (T a = - 40°C to 85°C; V CC = 2.7-3.6V) Symbol Parameter Test Conditions Min. Max. Unit I LI Input Leakage Current ± 2 µA I LO Output Leakage Current ± 2 µA I CC1 Standby Current CS# = V CC , V IN = V SS or V CC 5 µA I CC2 Deep Power-down Current CS# = V CC , V IN = V SS or V CC 5 µA CLK = 0.1 V CC / 0.9 V CC at 100MHz, DQ

• ESMT M12L64164A Elite Semiconductor Memory Technology Inc. Publication Date: May 2008 Revision: 3.3 25/46 12. About Burst Type Control Sequential Counting At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2, 4, 8 and full page. Basic MODE Interleave Counting At MRS A3 = “

• Hyundai H-HT5115-N, Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE 12 Pin Main Alt. Type Description 116 AL GPIO1 Analog Output 1) AUDIO DAC left channel output 2) TXD2 3) ASDATA1 4) GPIO_AL 117 ALS GPIO Analog Output 1) AUDIO DAC LS channel output 2) ALRCK 3) GPIO_ALS 118 ALF /CENTER GPIO Analog Output 1) AUDIO DAC CENTER channel output 2) Audio Mute 3) ASDATA0 4) GPIO_CENTER 119 ADACVDD1 Analog Power 3.3V power pin for audio DAC circuitry 120 ADACVDD2 Analog Power 3.3V power pin for audio DAC circuitry 121 AVDD12_1 Analog Power Analog 1.2V power 122 AGND12 Analog Gr

• Hyundai H-HT5115-N, This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 27 EN25F16 Rev. F, Issue Date: 2009 / 03 / 16 ABSOLUTE MAXIMUM RATINGS Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the m

• Hyundai H-HT5115-N, Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE 7 - Key shift up to +/- 8 keys - Chorus/Flanger/Harmony/Reverb  Channel equalizer  3D surround processing include virtual surround and speaker separation  TV Encoder  Four 108MHz/12bit DACs  Support NTSC, PAL-BDGHINM, PAL-60  Support 525p, 625p progressive TV format  Automatically turn off unconnected channels  Support Macrovision 7.1 L1, Macrovision 525P and 625P  CGMS-A/WSS  Closed Caption  Progressive Scan Video  Automatic detect film

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