Epson S1R75801F00A Technical Manual

Text of Epson S1R75801F00A User Guide:

• Epson S1R75801F00A, S1R72803F00A EPSON 51 Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x11 HW_Revision 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] R Indicate Hard Ware Revison Number 0x03 0x03 0x03 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] Hardware Revision Register The HW_Revision Register indicates the revision number of a chip. Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x18 LinkCtl_H 7: PassSelfID 0: Non PassSelfID 1: Self–ID to DMA FIFO 6: PassPhyPkt 0: Non Pass PHY Packet 1: PHY Pkt to DMA FIFO 5: PassBrPkt 0: Non Pass BusRst Packet 1: BusRst Pkt to DMA FIFO 4: EnPosWB R/W 0:

• Epson S1R75801F00A, S1R72803F00A EPSON 75 Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x54 RxDmaCtl 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 – 3: RxFIFOEpty R 0: Rx FIFO Empty 1: Non Empty 2: RxFIFOClr W 0: Normal 1: Rx FIFO Clear 1: RxMon R 0: Rx Stop 1: Rx Run 0: ForceBusy R/W 0: Normal 1: Busy Rx DMA Control Register Bit7..4 Reserved Bit3 Receive FIFO Empty When the DMA-FIFO for reception is empty, this bit becomes “0”. When it is not empty, it is “1”. This bit is read-only an

• Epson S1R75801F00A, S1R72803F00A 12 EPSON 7.2 IEEE1394 PACKET FORMAT 7.2.1 Transmit Packet Format (1) TxAsyncronousePacket <3> QuadReadReq, WriteResp (2) TxAsyncronousePacket <4> QuadWriteReq, QuadReadResp, BlockReadReq 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.07 1 2 DestinationID Sbid speed – –– tl rt pri ACK tcode (MSB) (MSB) (LSB) (LSB) PacketTypeSpecInfo reserved 1 QuadReadReq (tcode : 0x4) DestinationID DestinationOffset 1 2 rcode 2 WriteResp (tcode : 0x2) DestinationID reserved 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.07 1 2 3 Destination

• S1R72803F00A EPSON 9 Pin Name PIN I/O Reset Pin Function Remarks Other Pins ICEMD 179 I Hi-Impedance Control: Set Hi-Z Pull Down Resistor Integrated for all outputs. X2PSDX 155 I Double-speed mode setting pin HV DD Input HIGH : BCLK = CPU Clock LOW : BCLK = Half CPU Clock XNMI 177 I NMIInput Pin HV DD Input, Pull Up Resistor Integrated XRESET 178 I Initial Reset HV DD Input, Pull Up Resis

• Epson S1R75801F00A, S1R72803F00A 2 EPSON ● Built-in CPU Integration of a CPU eliminated the necessity of an external CPU to control this IC. CPU core: 32-bit RISC CPU S1C33000 Harvard architecture (Concurrency of a fetch and load/store) High speed/high performance: Ready for operation with 25MHz Command set: 16-bit fixed length, 105 types of basic commands Execution cycle: Execution at one cycle/command regarding a main command AND/OR (MAC) operation: 16 bits × 16 bits + 64 bits, 2 clocks/ MAC CPU Register: 16 32-bit general registers and 5 32- bit special registers Mem

• Epson S1R75801F00A, S1R72803F00A EPSON 1 1. DESCRIPTION The S1R72801F00A is a LINK/Transaction controller based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It integrates a built-in CPU and Flash ROM, and also integrates a part of transaction functions into hardware. If you set a PageTable address and its size, it can automatically fetch subsequent PageTables and transmit data. It can offer a 1394 interface optimum to computer peripherals in combination with the Cable PHY Transceiver Arbiter based on the above standard. The IDE interface complies with Ultra DMA mode 4 (ATA 66), offering a high transfer rate. 2. FEATURES ● LINK/Transaction Controller LINK Layer Ready for all two-way data tr

• S1R72803F00A EPSON 61 Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x31 SBP2Stat 7: FwPause R 0: Not Firmware Pause 1: FirmWre Pause 6: ErrPause R 0: Not Error Pause 1: Error Pause 5: NotQuadEnable R/W 0: Disable 1: Enable 4: WaitPLReady R 0: Not Ready 1: Ready 0x00 0x00 – 3: HwSBP2Exec R 0: Stop 1: Execute 2: PTaskExec R 0: Stop 1: Execute 1: StTaskExec R 0: Stop 1:

• Epson S1R75801F00A, S1R72803F00A EPSON 107 LED3 TLY124 CN5 1 2 4 3 D3V DSW4 SW DIP-2 10K R159 3 0 1 JUMP-3 JP3 C8 4.7K LED3 TLG124 TLG124 LED4 1K 1K R46 R47 R42 100p C7 5p 1 1 1 1 1 2 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 A18 A19 A20 A21 A22 A23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 138 137 136 135 134 133 132 131 13

• Epson S1R75801F00A, SPC7281F0A – i – Contents 1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. INTERNAL BLOCK DESCRIPTION .................................................................................................................. 3

• Epson S1R75801F00A, S1R72803F00A 74 EPSON Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x53 IsoDmaCtl 7: IsoChnlSel R/W 0: IsoTxPktHdr0 1: IsoTxPktHdr1 6: 0: 1: 5: 0: 1: 4: SelTxPtr R/W 0: Async Tx Pointer Select 1: ISO Tx Pointer Select 0x00 0x00 – 3: IsoFIFOEpty R 0: IsoFIFO Empty 1: Non Empty 2: IsoFIFOClr W 0: Normal 1: IsoFIFO Clear 1: IsoTxMon R 0: Iso Tx Stop 1: Iso Tx Run 0: IsoStart W 0: normal 1: Start ISO TxDMA Control Register Bit7 ISO Transmit Packet Header Channel Select Selects th

• S1R72803F00A 76 EPSON Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x55 AreaIndex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 – 3: MemMapIndex[3] 2: MemMapIndex[2] R/W Memory Map Area Index 1: MemMapIndex[1] 0: MemMapIndex[0] 0x56 AreaWindow_H 7: MemMapWindow[15] 6: MemMapWindow[14] 5: MemMapWindow[13] 4: MemMapWindow[12] 0x00 0x00 – 3: MemM

• Epson S1R75801F00A, S1R72803F00A EPSON 103 Symbol Specification Min. Typ. Max. Unit T 391 XHIOR → XHIOW ↑ Strobe stop time 50 – – ns T 392 HDMARQ ↓→ XHIOR OFF Constrained interlock time 0 – 100 ns T 393 XHIOR ↑ XHDMACK ↑ Mimimum interlock time 20 – – ns T 394 HDD(CRC) →XHDMACK ↑ CRC data setup time 6 – – ns T 395 XHDMACK ↑→ HDD(CRC) CRC data hold time 6 – – ns T 396 XHDMACK ↑→XHCS0,1 XHDMACK hold time 20 – – ns T 397 HIORDY ↑→XHIOR Last strobe time – – 60 ns T 398 HDMAQ ↓→ XHIOW Con

• Epson S1R75801F00A, S1R72803F00A 78 EPSON Bus Reset ORB Pointer Register This Bus Reset Header Pointer Register holds the value of a PostRxORBPtr when a bus reset occurs. When several bus resets occur, it is updated to the latest PostRxORBPtr. This register is read-only and writing to this register is ignored. Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x5A BRstORBPtr_H 7: Write is ignore 6: Read is always zero 5: 4: BusRstORBPtr[12] 0x00 0x00 – 3: BusRstORBPtr[11] 2: BusRstORBPtr[10] 1: BusRstORBPtr[9] 0: BusRstORBPtr[8] Bus Reset ORB-Data Area

• Epson S1R75801F00A, S1R72803F00A EPSON 31 Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x28 ChnlIndex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 – 3: Channel Index[3] 2: Channel Index[2] R/W ISO (Async Stream) Channel Index 1: Channel Index[1] 0: Channel Index[0] 0x29 ChnlWindow 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] R/W ISO (Async Stream) 0x00 0x00 – 3: Channel Window[3] Cahnnel Window 2: Channel Window[2] 1: Channel Window[1] 0: Channel Window[0] 0x2A CmprIndex 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 0x00 – 3: Compare Index[3] 2: Compare Index[2] R/W Compare Address Index 1: Compare Index[1] 0: Compare Index[0] 0x

• S1R72803F00A EPSON 5 5. PIN ASSIGNMENT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 LV DD N.C. DT0 DT1 HV DD DT2 DT3 DT4 DT5 DT6 DT7 DT8 V SS DT9 DT10 DT11 DT12 DT13 DT14 DT15 HV DD XWRH XWRL XRD AD0 AD1 AD2 AD3 V SS AD4 AD5 AD6 AD7 AD8 AD9 AD10 HV DD AD11 AD12 AD13 AD14 AD15 AD16 AD17 N.C. V SS 138 13

• Epson S1R75801F00A, S1R72803F00A EPSON 7 Pin Name PIN I/O Reset Pin Function Remarks IDE Interface (LVDD) HDA2 61 Otr Hi-Z (MSB) Drive Ability 2mA, Tristate HDA1 64 Otr Hi-Z IDE Address Signal Drive Ability 2mA, Tristate HDA0 62 Otr Hi-Z (LSB) Drive Ability 2mA, Tristate XHCS1 59 Otr Hi-Z IDE Chip Select Signal Drive Ability 2mA, Tristate XHCS0 60 Otr Hi-Z IDE Chip Select Signal Drive Ability 2mA, Tristate XHDASP 56 I – IDE DASP Signal 5V Tolerant, Schmitt Input XHRST 90 Otr Hi-Z IDE Reset Signal Drive Ability 2mA, Tristate C33 External Interface (HVDD) AD23 54 O (MSB) AD22 53 O AD21 52 O AD20 51 O AD19 50 O AD18 49 O AD17 44 O AD16 43 O AD15 42 O CPU

• Epson S1R75801F00A, S1R72803F00A EPSON 15 (3) RxAsyncronousePacket <6> BlockWriteReq, BlockReadResp, LockReq, LockResp (4) RxAsyncronousePhyPacket Normal (tcode : 0xE) (5) SelfIDPacket Received SelfID packets between BusReset and 1st-ArbRstGap (tcode : 0xE) 0 1 2 3 4 5 6 7 b.31 24 23 16 15 8 b.07 2 3 DestinationID SourceID DataLength speed tl BT 0 BC 0AS rt ACK pri tcode (MSB) (MSB) (LSB) (LSB) PacketTypeSpecInfo *DataPointer ExtendedTcode reserved 1 BlockWriteReq LockReq (tcode : 0x1) (tcode : 0x9) SourceID Destination

• Epson S1R75801F00A, S1R72803F00A EPSON 109 11. SHAPE OF PACKAGE 20 –0.1 22 –0.4 93138 20 –0.1 22 –0.4 47 92 INDEX 0.16 461 184 139 1.4 –0.1 0.1 1.7Max. 1 0.5 –0.2 0¡ 10¡ 0.125 0.4 +0.05 —0.03 +0.05 —0.02 5 Plastic QFP20-184 pin

• Epson S1R75801F00A, S1R72803F00A EPSON 67 Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x40 LinkRxHdrPtr_H 7: Write is ignore 6: Read is always zero 5: 4: LRHP[12] 0x00 0x00 – 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] R/W Current Received Packet Header Area Pointer 0: LRHP[8] 0x41 LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[5] 4: 0x00 0x00 – 3: Write is ignore 2: Read is always zero 1: 0: Receive Header LINK Pointer Register This Receive Header LINK Pointer Register indicates the starting address of the latest receive packet in the RxHeaderArea. Since the buffer pointer

• Epson S1R75801F00A, In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings. 4.5mm NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this mat

• Epson S1R75801F00A, S1R72803F00A 46 EPSON LINK Core Interrupt Status Register 0 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become “1” when the associated bit of the LINKIntEnb0 Register is “1”, this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Unknown Expected Channel When a packet of ISO channel not set in the CHANNEL_AVAILABLE Register is detected, this bit becomes “1”. It is enabled when the WonIRM = “1” of IRM IDSt

• Epson S1R75801F00A, S1R72803F00A 84 EPSON Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 0x00 0x00 – 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 0x00 0x00 – 3: ByteCount[19] 2: ByteCount[18] R/W IDE Data Transfer Byte Count Register 1: ByteCount[17] Read: Indicate Remain Byte Count 0: ByteCount[16] Write: Set Total Transfer Byte Count 0x6A IDE_ByteCount2 7: ByteCount[15] 6: ByteCount[14] 5: ByteCo

• Epson S1R75801F00A, S1R72803F00A EPSON 69 Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x4A UsedRxORBPtr_H 7: Write is ignore 6: Read is always zero 5: 4: UOP[12] 0x00 0x00 – 3: UOP[11] 2: UOP[10] 1: UOP[9] 0: UOP[8] 0x4B UsedRxORBPtr_L 7: UOP[7] R/W Received Packet ORB Data Area Used Pointer 6: UOP[6] 5: UOP[5] 4: UOP[4] 0x00 0x00 – 3: UOP[3] 2: UOP[2] 1: Write is ignore 0: Read is always zero Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x48 UsedRxHdrPtr_H 7: Write is ignore 6: Read always zero 5: 4: URHP[12] 0x00 0x00 �

• S1R72803F00A 30 EPSON Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x20 NODE_IDS_H 7: BusID[9] 6: BusID[8] 5: BusID[7] Serial Bus ID Number 4: BusID[6] Single Bus, Bus ID = 0x3FF 0xFF – – 3: BusID[5] R/W Multiple Bus, Bus ID is uniquely specifying 2: BusID[4] 1: BusID[3] 0: BusID[2] 0x21 NODE_IDS_L 7: BusID[1] – 6: BusID[0] – 5: PhyID[5] 1 4: PhyID[4]

• Epson S1R75801F00A, S1R72803F00A EPSON 65 Address Register Name Bit Symbol R/W D escription H.Rst S.Rst B.Rst 0x36 PayloadSize_H 7: 6: 5: 4: 0x00 0x00 – 3: Payload Size[11] Set Payload Size (Bytes) 2: Payload Size[10] If (HwSBP2Ctl.HwSBP2Exec ==0) { 1: Payload Size[9] Write is valid. 0: Payload Size[8] R/W } else { 0x37 PayloadSize_L 7: Payload Size[7] Write is invalid. 6: Payload Size[6] } 5: Payload Size[5] 4: Payload Size[4] 0x00 0x00 – 3: Payload Size[3] 2: Payload Size[2] 1: Payload Size[1] 0: Payload Size[0] Hardware SBP2

• Epson S1R75801F00A, S1R72803F00A EPSON 23 Address Register Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x30 HwSBP2Ctl PtNotPresen HOSTtoDev FromStream LastPT HwSBP2Rst HwSBP2Rsu HwSBP2Pau HwSBP2Star 0x31 HwSBP2Stat FwPause ErrPause NotQuadEnb WaitPLRead HwSBP2Exe PTaskExec StTaskExec TranExec 0x32 HwSBP2IntStat SplitTimeOut TxAckedIlleg TxAckMiss BRAbort NotQuad RxNotRespCm RxBroadCast RxAckDataErr 0x33 HwSBP2Index HwSBP2 Index 0x34 HwSBP2Window_H (MSB) HwSBP2 Window 0x35 HwSBP2Window_L (LSB) 0x36 PayloadSize_H (MSB) Payload Size 0x37 PayloadSize_L (LSB) 0x38 PageTableSize_H (MSB) Page Table Size 0x39 PageTableSize_L (LSB) 0x3A PageTableAdrs0 (MSB) 0x3B Pag

• Epson S1R75801F00A, S1R72803F00A 94 EPSON Symbol Description Unit Min. Max. T201 SCLK frequency 49.152MHz ± 100ppm T202 SCLK duty cycle % 45 55 T203 SCLK start → HCLK start delay time ns 5 15 T204 HCLK frequency MHz 20 24.576 T 205 HCLK duty cycle % 40 60 9.4 AC CHARACTERISTICS 9.4.1 Clock Timing 9.4.1.1 SCLK Timing 9.4.1.2 HCLK Timing T 201 SCLK HCLK T 202 T 204 T 205 T 205 T 203 T 202

• Epson S1R75801F00A, S1R72803F00A 34 EPSON Address Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst 0x40 LinkRxHdrPtr_H 7: Write is ignore 6: Read is always zero 5: 4: LRHP[12] 0x00 0x00 – 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] R/W Current Received Packet Header Area Pointer 0: LRHP[8] 0x41 LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[5] 4: 0x00 0x00 – 3: Write is ignore 2: Read is always zero 1: 0: 0x42 LinkRxORBPtr_H 7: Write is ignore 6: Read is always zero 5: 4: POP[12] 0x00 0x00 – 3: POP[11] 2: POP[10] 1: POP[9] 0: POP[8] 0x

• Epson S1R75801F00A, S1R72803F00A EPSON 59 Cycle Time Register Each of CycSecond, CycCount, and CycOffset Registers updates the timer by updating the current value of the cycle timer used for isochronous transfer. When the self node is a CYCLE MASTER, set the value of each register in the CYCLE START PACKET. When the self node is not a CYCLE MASTER, set the cycle_time_data of a received CYCLE START PACKET on each register. This register is enabled when LINKCtl(Hi). DisCycTimer=“0”. Reserve this register as a CycSecond(Hi) for WORD access. CYCLE_TIME.second_count This bit field indicates an integer at

• S1R72803F00A 102 EPSON Symbol Specification Min. Typ. Max. Unit T 381 XHCS0,1 ↑→XHDMACK ↓ Address setup time 20 – – ns T 382 HDMARQ ↑→XHDMACK ↓ XHDMACK response time 0 – – ns T 384 HDMACK ↓→HIORDY,XHIOW ↑ Envelope time 20 – 40 ns T 385 XHIOW ↓→XHIOR Constrained interlock time 0 – 100 ns T 386 XHIOR → HIORDY ↓ Unconstrained interlock time 0

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