Hitachi H8/3637 Hardware Manual

Text of Hitachi H8/3637 User Guide:

• Hitachi H8/3637, 353 TCSRW—Timer control/status register W H'B4 Watchdog timer Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/(W)* 5 B4WI 1 R 4 TCSRWE 0 R/(W)* 3 B2WI 1 R 0 WRST 0 R/(W)* 2 WDON 0 R/(W)* 1 B0WI 1 R Watchdog timer reset 1 0 [Clearing conditions] • Reset by RES pin • When 0 is written to WRST while writing 0 to B0WI when TCSRWE is set to 1 1 [Setting condition] When TCW overflows and an internal reset signal is generated Bit 0 write disable 1 0 Writing to bit 0 enabled 1 Writing to bit

• Hitachi H8/3637, 233 Bit 2—Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified. Bit 2: TEND Description 0 Indicates that transmission is in progress [Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE. • When data is written to TDR by an instruction. 1 Indicates that a transmission has ended (initial value) [Setting conditions] • When bit TE in SCR3 is cleared to 0. • If TDRE is set to 1 when the last bit of a transmitted character is sent. Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 ho

• Hitachi H8/3637, 367 SYSCR1—System control register 1 H'F0 System control Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 3 LSON 0 R/W 0 — 1 — 2 — 1 — 1 — 1 — 4 STS0 0 R/W Software standby 0 When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. 1 Standby timer select 2 to 0 0 Wait time = 8,192 states Wait time = 16,384 states 0 0 1 Wait time = 32,768 states Wait time = 65,536 states 10 1 1 * Wait time = 131,072 states Low speed on flag 0 The CPU ope

• Hitachi H8/3637, 293 Section 13 14-bit Pulse Width Modulator (PWM) 13.1 Overview The H8/3637 Series is provided with a 14-bit pulse width modulator (PWM). The PWM can be used as a D/A converter by connecting a low-pass filter. 13.1.1 Features Features of the 14-bit PWM are given below. • Choice of two conversion periods • A conversion period of 32,768/ø with a minimum transition width of 2/ø, or a conversion period of 16,384/ø with a minimum transition width of 1/ø, can be selected. • Pulse-division method to reduce ripple 13

• 255 Transmitting: Figure 10.14 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR TDRE = 1? Write transmit data in TDR Continue data transmission? Read bit TEND in SSR TEND = 1? Write 0 to bit TE in SCR3 End No Yes No Yes No Yes 1 2 1. 2. Read the serial status register (SSR), and after confirmi

• Hitachi H8/3637, 337 PMR1—Port mode register 1 H'98 I/O ports Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 TMIG 0 R/W 0 TMOW 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W P1 /TMOW pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOW output pin P1 /TMIG pin function switch 0 Functions as P1 I/O pin 1 Functions as TMIG input pin P1 /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin P1 /TMOFH pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFH output

• 260 Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, first confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2. To switch from receiving to simultaneous transmitting and receiving, after confirming that SCI3 has finished receiving, clear RE to 0. Next, after confirming that RD

• Hitachi H8/3637, 126 Table 8.3 Port 1 Pin Functions (cont) Pin Pin Functions and Selection Method P1 3 /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 3 in PCR1. TMIG 0 1 PCR1 3 01 * Pin function P1 3 input pin P1 3 output pin TMIG input pin P1 2 /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 2 in PCR1. TMOFH 0 1 PCR1 2 01 * Pin function P1 2 input pin P1 2 output pin TMOFH output pin P1 1 /TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR1 1 in PCR1. TMOFL 0 1 PCR1 1 01 * Pin function P1 1 input pin P1 1 output pin TMOFL output

• 351 DTCR—DTMF control register H'B2 DTMF generator Bit Initial value Read/Write 7 DTEN 0 R/W 6 — 1 — 5 CLOE 0 R/W 4 RWOE 0 R/W 3 CLF1 0 R/W 0 RWF0 0 R/W 2 CLF0 0 R/W 1 RWF1 0 R/W DTMF row signal output frequency 1 and 0 RWF0 0 1 0 1 DTMF row signal output frequency 697 Hz (R1) 770 Hz (R2) 852 Hz (R3) 941 Hz (R4) Row output enable 0 1 DTMF row signal output is disabled (high-imped

• Hitachi H8/3637, 134 Table 8.6 Port 2 Pin Functions (cont) Pin Pin Functions and Selection Method P2 2 /SI 1 The pin function depends on bit SI1 in PMR2 and bit PCR2 2 in PCR2. SI1 0 1 PCR2 2 01 * Pin function P2 2 input pin P2 2 output pin SI 1 input pin P2 1 /SCK 1 The pin function depends on bit SCK1 in PMR2, bit CKS3 in SCR1, and bit PCR2 1 in PCR2. SCK1 0 1 CKS 3 * 01 PCR2 1 01** Pin function P2 1 input pin P2 1 output pin SCK 1 output pin SCK 1 input pin P2 0 /IRQ 4 / ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit PCR2 0 in PCR2. IRQ4 0 1 PCR2 0 01 * TRGE * 01 Pin function P2 0 input pin P2 0 output pin IRQ 4 inp

• Hitachi H8/3637, 79 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4.1 shows a block diagram of the clock pulse generators. System clock oscillator System clock divider (1/2) Subclock oscillator Subclock divider (1/2, 1/4, 1/8) System clock divider (1/8) System clock pulse generator Subclock pulse generator Prescaler S (13 bits) Prescal

• 358 ICRGF—Input capture register GF H'BD Timer G Bit Initial value Read/Write 7 ICRGF7 0 R 6 ICRGF6 0 R 5 ICRGF5 0 R 4 ICRGF4 0 R 3 ICRGF3 0 R 0 ICRGF0 0 R 2 ICRGF2 0 R 1 ICRGF1 0 R ICRGR—Input capture register GR H'BE Timer G Bit Initial value Read/Write 7 ICRGR7 0 R 6 ICRGR6 0 R 5 ICRGR5 0 R 4 ICRGR4 0 R 3 ICRGR3 0 R 0 ICRGR0 0 R 2 ICRGR2 0 R 1 ICRGR1 0 R

• Hitachi H8/3637, 324 Table A.2 Operation Code Map High Low 0123456789ABCDEF 0 1 2 3 4 5 6 7 8 9 A B C D E F NOP BRA MULXU BSET SHLL SHAL SLEEP BRN DIVXU BNOT SHLR SHAR STC BHI BCLR ROTXL ROTL LDC BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV * Note: Bit-manipulation instructions The PUSH and POP instructions are identical in machine la

• 57 Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3637 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling High Reset Exception handling starts as soon as the reset state is c

• 190 • Timing with noise canceller function enabled When input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. Figure 9.10 shows the timing. External input capture signal Sampling clock Noise canceller circuit outp

• Hitachi H8/3637, 121 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration. P1 7 /IRQ 3 /TMIF P1 6 /IRQ 2 /TMCIY P1 5 /IRQ 1 P1 4 /PWM P1 3 /TMIG P1 2 /TMOFH P1 1 /TMOFL P1 0 /TMOW Port 1 Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbrev. R/W Initial Value Address Port data register 1 PDR1 R/W H'00 H'FFD4 Port control register 1 PCR1 W H'00 H'FFE4 Port pull-up control register 1 PUCR1 R/W H'00 H'FF9C Port mode register 1 PMR1 R/W H'10 H'FF98

• Hitachi H8/3637, 232 Bit 4: Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4: FER Description 0 Indicates that data receiving is in progress or has been completed * 1 (initial value) [Clearing condition] After reading FER = 1, cleared by writing 0 to FER 1 Indicates that a framing error occurred in data receiving [Setting condition] The stop bit at the end of receive data is checked and found to be 0 * 2 Notes: 1. When bit RE in serial cont

• Hitachi H8/3637, 174 9.3.3 Interface with the CPU TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it makes use of an 8-bit temporary register (TEMP). In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte size MOV instructions, and always access the upper byte first. Data will not be transferred properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such restriction on the order of access. Wr

• Hitachi H8/3637, 342 SCSR1—Serial control/status register 1 H'A1 SCI1 Bit Initial value Read/Write 7 — 1 — 6 SOL 0 R/W 5 ORER 0 R/(W) 4 — 1 — 3 — 1 — 0 STF 0 R/W 2 — 1 — 1 — 0 R Extended data bit Overrun error flag 0 Read Write * Start flag 0 Indicates that transfer is stopped Invalid 1 Read Write Read Write Indicates transfer in progress Starts a transfer operation 1 Read Write SO 1 pin output level is low SO 1 pin output level changes to low SO 1 pin output level is high SO 1 pin output level changes to high Note: Only a write of 0 for flag cl

• Hitachi H8/3637, 257 Receiving: Figure 10.16 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start Read bit OER in SSR Read bit RDRF in SSR Read received data in RDR OER = 1? Continue receiving? Clear bit RE in SCR3 to 0 End Clear bit OER in SSR to 0 1 3 4 4 2. 3. 4. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 1. Read bit

• Hitachi H8/3637, 149 8.8 Port 9 8.8.1 Overview Port 9 is an 8-bit I/O port configured as shown in figure 8.7. P9 P9 P9 P9 P9 P9 P9 P9 7 6 5 4 3 2 1 0 Port 9 Figure 8.7 Port 9 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 9 register configuration. Table 8.20 Port 9 Registers Name Abbrev. R/W Initial Value Address Port data register 9 PDR9 R/W H'00 H'FFDC Port control register 9 PCR9 W H'00 H'FFEC

• Hitachi H8/3637, 320 Table A.1 Instruction Set (cont) Mnemonic Operation Addressing Mode/ Instruction Length (Bytes) Operand Size #xx: 8/16 Rn @Rn @(d:16, Rn) @–Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States IHNZVC Condition Code ↔ BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAN

• Hitachi H8/3637, 282 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. Internal data bus AMR ADSR ADRR Control logic + – Com- parator AN 4 AN 5 AN 6 AN 7 ADTRG AV CC AV SS Multiplexer Reference voltage IRRAD AV CC AV SS Legend: AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D converter interrupt request flag Figure 12.1 Block Diagram of the A/D Converter

• Hitachi H8/3637, 143 8.6 Port 7 8.6.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.5. P7 P7 P7 P7 P7 P7 P7 P7 7 6 5 4 3 2 1 0 Port 7 Figure 8.5 Port 7 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 7 register configuration. Table 8.14 Port 7 Registers Name Abbrev. R/W Initial Value Address Port data register 7 PDR7 R/W H'00 H'FFDA Port control register 7 PCR7 W H'00 H'FFEA

• Hitachi H8/3637, 10 Table 1.2 Pin Functions (cont) Pin No. Type Symbol TFP-80F TFP-80C FP-80B I/O Name and Functions I/O ports PB 7 to PB 4 76 to 79 78 to 80, 1 Input Port B: This is a 4-bit input port PA 3 to PA 0 27 to 30 29 to 32 I/O Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). PE 3 , PE 2 72, 71 74, 73 I/O Port E: This is a 2-bit I/O port. Input or output can be designated for each bit by means of port control register E (PCRE). P1 7 to P1 0 17 to 24 19 to 26 I/O Port 1: This is an 8-bit I/O port. Inpu

• Hitachi H8/3637, 113 Figure 6.5 shows a program/verify timing diagram. Address Data V PP V CC CE PGM OE V PP V CC V CC V CC Program Verify Input data Output data t AS t DS t VPS t VCS t CES t PW t OPW * t DH t OES t OE t DF t AH Note: * t OPW is defined by the value given in the high-speed, high-reliability programming flow chart in figure 6.4. +1 Figure 6.5 PROM Program/Verify Timing

• Hitachi H8/3637, 78 Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alt

• Hitachi H8/3637, 227 Serial Control Register 3 (SCR3) Bit 76543210 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any time. SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7—Transmit Interrupt Enable (TIE): Bit 7 enables or disables the transmit dat

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