Hitachi HD6473867 Hardware Manual
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Hitachi HD6473867, CWOSR—Subclock Output Select Register H'92 Timer A Bit Initial value Read/Write 7 — 1 R 6 — 1 R 5 — 1 R 0 CWOS 0 R/W 2 — 1 R 1 — 1 R 4 — 1 R TMOW pin clock select 0 Clock output from TMA is output 1ø W is output 3 — 1 R 402
Hitachi HD6473867, SMR32—Serial mode register 32 H'A8 SCI32 Bit Initial value Read/Write 7 COM32 0 R/W 6 CHR32 0 R/W 5 PE32 0 R/W 0 CKS320 0 R/W 2 MP32 0 R/W 1 CKS321 0 R/W 4 PM32 0 R/W Clock select 0 0 01 1 1 1 ø clock øw/2 clock 0 ø/16 clock ø/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and ch
Hitachi HD6473867, Table A-3 Number of Cycles in Each Instruction Execution Status Access Location (instruction cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch S I 2— Branch address read S J Stack operation S K Byte data access S L 2 or 3* Word data access S M — Internal operation S N 1 Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details. 390
Hitachi HD6473867, 9. Switching SCK 3 function If pin SCK 3 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (ø) cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK 3 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK 3 from
336 13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. 1. Hardware settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V 2 and V 3 as shown in figure 13-3. Figure 13-3 Handling of LCD Drive Power Supply when Using 1/2 Duty b. Large-panel display As the impedance
Hitachi HD6473867, Figure F-3 TFP-80C Package Dimensions Hitachi Code JEDEC EIAJ Weight (reference value) TFP-80C — Conforms 0.4 g Unit: mm *Dimension including the plating thickness Base material dimension 0.10 M 0.10 0.5 ± 0.1 0° – 8° 1.20 Max 14.0 ± 0.2 0.5 12 14.0 ± 0.2 60 41 120 80 61 21 40 *0.17 ± 0.05 1.0 *0.22 ± 0.05 0.10 ± 0.10 1.00 1.25 0.20 ± 0.04 0.15 ± 0.04 475
Hitachi HD6473867, Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is
Hitachi HD6473867, 290 • Simultaneous transmit/receive Figure 10-15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Figure 10-15 Example of Simultaneous Data Transmission/Reception Flowchart(Synchronous Mode) Start End Read bit TDRE in SSR Sets bits SPC31 and SPC32 to 1 in SPCR 1 2 3 4 Write transmit data to TDR Read bit OER in SSR Read bit RDRF in SSR Clear bits TE and RE to 0 in SCR3 Yes TDRE = 1? No OER = 1? No RDRF = 1? Yes
Hitachi HD6473867, 2.9 Application Notes........................................................................................................... 53 2.9.1 Notes on Data Access......................................................................................... 53 2.9.2 Notes on Bit Manipulation.................................................................................. 55 2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 61 Section 3 Exception Handling................................................
Hitachi HD6473867, TCC—Timer counter C H'B5 Timer C TLC—Timer load register C H'B5 Timer C Bit Initial value Read/Write 7 TLC7 0 R/W 6 TLC6 0 R/W 5 TLC5 0 R/W 4 TLC4 0 R/W 3 TLC3 0 R/W 0 TLC0 0 R/W 2 TLC2 0 R/W 1 TLC1 0 R/W Reload value Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 0 TCC0 0 R 2 TCC2 0 R 1 TCC1 0 R Count value 420
Hitachi HD6473867, When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000. Bit 7 OVH Description 0 ECH has not overflowed (initial value) Clearing conditions: After reading OVH = 1, cleared by writing 0 to OVH 1 ECH has overflowed Setting conditions: Set when ECH overflows from H’FF to H’00 Bit 6: Counter overflow flag L (OVL) Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by reading it
Hitachi HD6473867, 10.2.8 Bit rate register (BRR) BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode. Table 10-3 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10-3 Examples of BRR Settings for Various Bi
11 Table 1-2 Pin Functions (cont) Pin No. FP-80A Type Symbol TFP-80C FP-80B I/O Name and Functions Serial RXD 31 22 24 Input SCI3-1 receive data input: communi- This is the SCI31 data input pin. cation TXD 31 23 25 Output SCI3-1 transmit data output: interface This is the SCI31 data output pin. (SCI) SCK 31 21 23 I/O SCI3-1 clock I/O: This is the SCI31 clock I/O pin. RXD 32 70 72 Input SCI3-2
2. Power supply voltage and operating frequency range 16.384 8.192 4.096 1.8 3.6 5.5 V CC (V) øSUB (kHz) 19.2 9.6 4.8 3.0 1.0 1.6 2.0 0.2 0.5 1.8 2.2 3.0 2.6 4.5 5.5 V CC (V) V CC (V) ø (MHz)ø (MHz) 375 125 200 250 4.096 62.5 1.8 2.2 3.0 2.6 4.5 5.5 V CC (V) ø (kHz) 0.5 1.0 0.2 1.8 2.2 5.5 VCC (V) ø (kHz) 62.5 125 4.096 1.8 2.2 5.5 • Active (medium-speed) mode (except A/D conver
Hitachi HD6473867, Figure F-2 FP-80B Package Dimensions Hitachi Code JEDEC EIAJ Weight (reference value) FP-80B — — 1.7 g Unit: mm *Dimension including the plating thickness Base material dimension 0.15 M 0° – 10° *0.37 ± 0.08 *0.17 ± 0.05 3.10 Max 1.2 ± 0.2 24.8 ± 0.4 20 64 41 40 25 24 1 80 65 18.8 ± 0.4 14 0.15 0.8 2.70 2.4 0.20 +0.10 –0.20 0.8 1.0 0.35 ± 0.06 0.15 ± 0.04 474
Hitachi HD6473867, SSR32—Serial status register 32 H'AC SCI32 Bit Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. 7 TDRE32 1 R/(W) 6 RDRF32 0 R/(W) 5 OER32 0 R/(W) 0 MPBT32 0 R/W 2 TEND32 1 R 1 MPBR32 0 R 4 FER32 0 R/(W) Receive data register full 0 There is no receive data in RDR32 [Clearing conditions] • After reading RDRF32 = 1, cleared by writing 0 to RDRF32 • When RDR32 data is read by an instruction 1 There is receive data in RDR32 [Setting conditions] When reception ends normally and receive data is transferred from RSR32 to RDR32 Transmit data register empty 0 Transmit data written in TDR32 has not been transferred to TSR3
Hitachi HD6473867, Figure 10-8 Example of Data Reception Flowchart (Asynchronous Mode) (cont) Start receive error processing End of receive error processing 4 Clear bits OER, PER, FER to 0 in SSR Yes OER = 1? Yes Yes FER = 1? Break? Yes PER = 1? No No No No Overrun error processing Framing error processing (A) Parity error processing If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Reception cannot be resumed if any of
Hitachi HD6473867, Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2. When switching from reception to simultaneous transmission/reception, check that SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1 simultaneously. 10.3.4 Multiprocessor Communic
1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3864 Series. Table 1-2 Pin Functions Pin No. FP-80A Type Symbol TFP-80C FP-80B I/O Name and Functions Power V CC 32 34 Input Power supply: All V CC pins should be source pins CV CC 26 28 connected to the system power supply. See section 14, Power Supply Circuit. V SS 5 7 Input Ground: All V SS pins should be 27 29 connected to
Hitachi HD6473867, Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 0 1 stop bit *1 (initial value) 1 2 stop bits *2 Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character. In reception, only the fi
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