Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY Datasheet
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Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY, DATASHEET The Cadence integrated high-speed design and analysis environment streamlines creation of high-speed interconnect on digital printed circuit board (PCB) systems. A range of capabilities—from simple to advanced—enable electrical engineers to explore, optimize, and resolve issues related to electrical performance at all stages of the design cycle. By enabling a constraint-driven design flow, this unique environment accelerates the time to first-pass design success while reduc
Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY, 2 www.cadence.com CADENCE PCB SIGNAL AND POWER INTEGRITY Figure 1: No translation is required to analyze selected signals from the physical board or extract them into the SigXplorer module. Analysis results are reported in the same constraint manager used by Allegro PCB Editor. Coupled differential pairs and nets extended through discrete components (x-nets) are automatically identified, analyzed, and/or extracted. CONSTRAINT-DRIVEN DESIGN METHODOLOGY Cadence PCB SI technology works seam- lessly with the constraint management system of th
3 www.cadence.com CADENCE PCB SIGNAL AND POWER INTEGRITY display (See Figure 3.) or in a report that shows voltage drop at any pin that is marked as a current sink. Users can also view relative and absolute voltage drop at any point on the net. AC power integrity is accomplished with Allegro PCB PI, an option to Allegro PCB SI. Its unique, integrated design and anal- ysis environmen
Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY, 4 www.cadence.com CADENCE PCB SIGNAL AND POWER INTEGRITY can perform serial link analysis more thoroughly and more efficiently than with proprietary tools supplied by semiconduc- tor and SerDes vendors. SOURCE SYNCHRONOUS BUS ANALYSIS METHODOLOGY Allegro PCB SI provides a quick and easy methodology to perform post-layout analysis of all the signals associated with a source synchronous bus. It shortens the time to simulate various configurations (read/write, active, idle) associated wi
Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY, 5 www.cadence.com CADENCE PCB SIGNAL AND POWER INTEGRITY PCB SI product comparison grid (OrCAD, Allegro L/XL/GXL) OrCAD Signal Explorer Allegro PCB SI L Allegro PCB SI XL Allegro PCB SI GXL Macro modeling support (DML) • • • • IBIS 4.2 support • • • • IBIS ICM model support • • • • Spectre-to-DML • • • • HSPICE-to-IBIS • • • • Graphical topology editor • • • • Lossy transmission lines • • • • Coupled (3 net) simulation • • • • Differential pair exploration and simulation • • • • Custom stimulus • • • Topology append • �
Cadence CADENCE PCB SIGNAL AND POWER INTEGRITY, © 2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Allegro, OrCAD, and SourceLink are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. 20808/7430 11/08 MK/MVC/CS/PDF PCB SI product comparison grid (OrCAD, Allegro L/XL/GXL) OrCAD Signal Explorer Allegro PCB SI L Allegro PCB SI XL Allegro PCB SI GXL Coupled via model generator for pre-layout explorations S-Parameters S-Parameters • High-capacity channel simulation Serial Link Serial Link
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