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Cypress Semiconductor AN6077 Specification Sheet

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Cypress Semiconductor AN6077 User Manual
Cypress Semiconductor AN6077 User Guide
Cypress Semiconductor AN6077 Online Manual

Text of Cypress Semiconductor AN6077 User Guide:

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 1 with FX2LP Implementing an 8-Bit Asynchronous Interface Application Note Abstract This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB FX2LP™ to implement an 8-bit asynchronous interface. The GPIF is a programmable 8 or 16-bit parallel interface that reduces system costs by providing a glueless interface between the EZ-USB FX2LP and different types of external peripherals. The GPIF allows the EZ-USB FX2LP to perform local bus mastering to external peripherals implementing a wide variety

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 2 AN6077 GPIF Master Pin Descriptions The GPIF pin names, descriptions, and their uses are dis- cussed in this section. RDYn Inputs RDY[5:0] are ‘ready’ inputs that can be sampled and allow a transaction to wait (inserting wait states), continue, or repeat until the signal is at the appropriate level. This implementa- tion uses RDY0 and RDY1 to control data flow. RDY0 is tied to FLAGC (EP2 Empty Flag) of the slave and RDY1 is tied to FLAGB (EP6 Full Flag) of the slave. Other RDY inputs may be used in the application for addi- tional de

  • February 19, 2008 Document No. 001-15342 Rev. ** 3 AN6077 Figure 2 shows the GPIF Designer view of the FIFO Read waveform. FIFOWR When creating the FIFOWR waveform the following timing parameters must be met. tWR pwl - SLWR Pulse Width LOW = 50 ns (minimum) tWR pwh - SLWR Pulse Width HIGH = 50 ns (minimum) tSFD - SLWR to FIFO DATA Setup Time= 10 ns (mini- mum) tFDH - FIFO DATA to SLWR Hold Ti

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 4 AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write Waveform in gpif.c 8051 Firmware Programming (Master) This section describes how to configure the 8051 to support the interface on the master side (register settings and others) and discusses the firmware implemented to perform data transactions over the local bus and the USB. The complete code listing is provided at the end of this document. Firmware Architecture The firmware is designed to handle USB INs and OUTs arbi- trarily (for example, the direction of transfer is not favored). It is also fairly deterministic in i

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 5 AN6077 The firmware uses the AUTO mode for both IN and OUT transfers. This means that the maximum size (512 bytes) packets are committed automatically from the peripheral domain to the USB domain for OUT transfers. For IN trans- fers, they are committed from USB to the peripheral domain. The 8051 is not involved in committing packets. Short pack- ets are handled by the master strobing the PKTEND of the slave. In this implementation, the PKTEND of the slave is tied to CTL2 of the master. So the GPIFIDLECTL register is writ- ten to strobe P

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 6 AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL ); // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s) SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // once master (GPIF) drains OUT packet, it (re)arms to usb domain // this path is always auto, meaning core handles it if( xFIFOTC_OUT < enum_pkt_size )

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 7 AN6077 if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full" } else { // EP6FF=0, when fifo "not full", for example, buffer available // setup GPIF transaction count SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY; EP6GPIFTCL = 0x00; // trigger FIFO read transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // wait for trans

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 8 AN6077 Code Listing for Master Side #pragma NOIV // Do not generate interrupt vectors #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.h" // SYNCDELAY macro extern BOOL GotSUD; // Received setup data flag extern BOOL Sleep; extern BOOL Rwuen; extern BOOL Selfpwr; BYTE Configuration; // Current configuration BYTE AlternateSetting; // Alternate settings // proto's from "gpif.c" void GpifInit( void ); // 512 for high speed, 64 for full speed static WORD enum_pkt_size = 0x0000; // when set firmware running in T

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 9 AN6077 // EP4 and EP8 are not used in this implementation SYNCDELAY; // EP4CFG = 0x20; // clear valid bit SYNCDELAY; // EP8CFG = 0x60; // clear valid bit SYNCDELAY; // FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions SYNCDELAY; // FIFORESET = 0x82; // reset, FIFO 2 SYNCDELAY; // FIFORESET = 0x84; // reset, FIFO 4 SYNCDELAY; // FIFORESET = 0x86;

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 10 AN6077 } #define GPIFTRIGWR 0 #define GPIFTRIGRD 4 #define GPIF_EP2 0 #define GPIF_EP4 1 #define GPIF_EP6 2 #define GPIF_EP8 3 void TD_Poll( void ) { // Called repeatedly while the device is idle static WORD xFIFOTC_OUT = 0x0000; static WORD xFIFOTC_IN = 0x0000; // Registers which require a synchronization delay, see section 15.14 // FIFORESET FIFOPINPOLAR // INPKTEND OUTPKTEND // EPxBCH:L REVCTL // GPIFTCB3 GPIFTCB2 // GPIFTCB1 GPIFTCB0 // EPxFIFOPFH:L EPxAUTOINLENH:L // EPxFIFOCFG EPxGPIFFLGSEL // PINFLAGSxx E

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 11 AN6077 // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // once master (GPIF) drains OUT packet, it (re)arms to usb domain // this path is always auto, meaning core handles it if( xFIFOTC_OUT < enum_pkt_size ) {

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 12 AN6077 // RDY0=1, when peripheral is "not empty" // drive FIFOADDR lines OEA = 0xC0; IOA = 0x00; if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full" } else { // EP6FF=0, when fifo "not full", for example, buffer available // setup GPIF transaction count SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY;

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 13 AN6077 } BOOL TD_Suspend( void ) { // Called before the device goes into suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after the device resumes return( TRUE ); } //----------------------------------------------------------------------------- // Device Request hooks // The following hooks are called by the end point 0 device request parser. //----------------------------------------------------------------------------- BOOL DR_GetDescriptor( void ) { return(

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 14 AN6077 { // Called when a Set Interface command is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRUE ); // Handled by user code } BOOL DR_GetStatus( void ) { return( TRUE ); } BOOL DR_ClearFeature( void ) { return( TRUE ); } BOOL DR_SetFeature( void ) { return( TRUE ); } //----------------------------------------------------------------------------- // USB Interrupt Handlers // The following functions are called by the USB in

  • February 19, 2008 Document No. 001-15342 Rev. ** 15 AN6077 EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear URES IRQ } void ISR_Susp( void ) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmSUSP; } void ISR_Highspeed( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFu

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 16 AN6077 } void ISR_Ep1pingnak( void ) interrupt 0 { } void ISR_Ep2pingnak( void ) interrupt 0 { } void ISR_Ep4pingnak( void ) interrupt 0 { } void ISR_Ep6pingnak( void ) interrupt 0 { } void ISR_Ep8pingnak( void ) interrupt 0 { } void ISR_Errorlimit( void ) interrupt 0 { } void ISR_Ep2piderror( void ) interrupt 0 { } void ISR_Ep4piderror( void ) interrupt 0 { } void ISR_Ep6piderror( void ) interrupt 0 { } void ISR_Ep8piderror( void ) interrupt 0 { } void ISR_Ep2pflag( void ) interr

  • February 19, 2008 Document No. 001-15342 Rev. ** 17 AN6077 } void ISR_Ep8fflag( void ) interrupt 0 { } void ISR_GpifComplete( void ) interrupt 0 { } void ISR_GpifWaveform( void ) interrupt 0 { // FIFORd WF detected peripheral prematurely empty (less than max. pkt. size) GPIFABORT = 0xFF; // abort to handle shortpkt INPKTEND = 0x06; SYNC

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 18 AN6077 // PINFLAGSxx EPxFIFOIRQ // EPxFIFOIE GPIFIRQ // GPIFIE GPIFADRH:L // UDMACRCH:L EPxGPIFTRIG // GPIFTRIG SYNCDELAY; FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions SYNCDELAY; // see TRM section 15.14 FIFORESET = 0x82; // reset, FIFO 2 SYNCDELAY; // FIFORESET = 0x84; // reset, FIFO 4 SYNCDELAY; // FIFORESET = 0x86; // reset, FIFO 6 SYNCDELAY; // FIFORESET = 0x88;

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 19 AN6077 EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0 SYNCDELAY; EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 SYNCDELAY; } void TD_Poll( void ) { // Called repeatedly while the device is idle // nothing to do;slave fifo's are in AUTO mode } BOOL TD_Suspend( void ) { // Called before the device goes into suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after the device resumes return( TRUE ); } //----------------------------------------------------------------------------- // Device Request hooks // The following hooks are

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 20 AN6077 EP0BUF[ 0 ] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_SetInterface( void ) { // Called when a Set Interface command is received AlternateSetting = SETUPDAT[ 2 ]; return( TRUE ); // Handled by user code } BOOL DR_GetInterface( void ) { // Called when a Set Interface command is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRU

  • February 19, 2008 Document No. 001-15342 Rev. ** 21 AN6077 USBIRQ = bmSOF; // Clear SOF IRQ } void ISR_Ures( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr; } else { pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr; } EZUSB_IR

  • Cypress Semiconductor AN6077, February 19, 2008 Document No. 001-15342 Rev. ** 22 AN6077 } void ISR_Ep4inout( void ) interrupt 0 { } void ISR_Ep6inout( void ) interrupt 0 { } void ISR_Ep8inout( void ) interrupt 0 { } void ISR_Ibn( void ) interrupt 0 { } void ISR_Ep0pingnak( void ) interrupt 0 { } void ISR_Ep1pingnak( void ) interrupt 0 { } void ISR_Ep2pingnak( void ) interrupt 0 { } void ISR_Ep4pingnak( void ) interrupt 0 { } void ISR_Ep6pingnak( void ) interrupt 0 { } void ISR_Ep8pingnak( void ) interrupt 0 { } void ISR_Errorlimit( void ) interrupt 0 { } void ISR_Ep2piderror( void ) interrupt 0 { } void ISR_Ep4piderror( void ) interrupt 0 { } void ISR_Ep6piderror( void ) interrupt 0 { } voi

  • AN6077 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com © Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. N

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