Cypress Semiconductor EZ-USB FX2 PCB Design Manual
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Cypress Semiconductor EZ-USB FX2 PCB, November 21, 2002 Document No. 001-43117 Rev. ** 1 EZ-USB FX2™ PCB Design Recommendations Introduction This application note presents recommendations for design- ing with the Cypress Semiconductor EZ-USB FX2™ compo- nent. Techniques for high-speed design should be applied to circuits using the EZ-USB FX2. Due to the packaging and high performance characteristics of the EZ-USB FX2, consid- eration of the PCB thermal design is required. CY4611 EZ-USB FX2 USB to ATA Reference Design A complete
Cypress Semiconductor EZ-USB FX2 PCB, November 21, 2002 Document No. 001-43117 Rev. ** 2 AN1196 Figure 2. FX2 Eye Diagram of High-speed Signaling In the diagram, notice how no signal traces overlap the cen- tral, six-sided, shaded area. Also, no trace overlaps the extremes of permissible voltage as shown in the shaded lines at the very top and very bottom of the figure. Overlap of sig- nal trace over the shaded areas would be a violation of the USB 2.0 specification. Overlap can be caused by excessive data jitter, mismatched impedance, and improper EMI filter- ing. The Cypress Semicondu
Cypress Semiconductor EZ-USB FX2 PCB, November 21, 2002 Document No. 001-43117 Rev. ** 3 AN1196 Maintain PCB Trace Impedance Designing the PCB traces for particular characteristic imped- ance is very important to signal quality. The USB specification requires controlled impedance among all elements in the USB data path. The differential impedance of each USB data pair should be 90 ohms with a 10% tolerance to match the differential output impedance of high-speed capable drivers. A common way to implement a differential pair is to use an edge-coupled, surface micro-strip line. The pair is pla
Cypress Semiconductor EZ-USB FX2 PCB, November 21, 2002 Document No. 001-43117 Rev. ** 4 AN1196 This figure shows the dielectric material thickness (“Prepreg”) between layers 1 and 2 and the thickness between layers 3 and 4. The dimensions between these layers are a key ele- ment in the design to set the proper characteristic impedance for the USB data traces. This is the “h” term mentioned in the prior section on PCB impedance design. The core material of the PCB lies between layer 2 and 3. Although this material is not critical to impedance charac
November 21, 2002 Document No. 001-43117 Rev. ** 5 AN1196 The design of the land area for the exposed paddle is critical to proper thermal transfer. A copper fill is to be designed into the PCB and under the QFN in order to assist thermal trans- fer. Figure 5 is the diagram of the PCB land area for the EZ- USB FX2. Figure 5. Diagram of the PCB Land Area The heat is transferred
Cypress Semiconductor EZ-USB FX2 PCB, November 21, 2002 Document No. 001-43117 Rev. ** 6 AN1196 EZ-USB FX2 Assembly Recommenda- tions The solder stencil over the exposed paddle is required to per- mit at least 50% solder application coverage. Figure 8 is a graph from Amkor research showing how solder void much less than 50% has little influence on thermal transfer. The package is a smaller one than the EZ-USB FX2 8-mm 56- lead package, but the values do scale. Figure 8. Thermal Performance versus Solder Void The manufacturing processes and practices of the assembly operation govern the stencil pattern used. Generally, arrays of either round or square patterns are used. A circular stencil was
Cypress Semiconductor EZ-USB FX2 PCB, AN1196 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications,
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