ELANsat Tech EM78P156N Specification
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ELANsat Tech EM78P156N, EM78P156N OTP ROM 3. PIN ASSIGNMENTS TCC VDDVss P50 P51 P53 P60/INT P61 P62 P63 P64 P52 /RESET OSCI OSCO P67 P66 P65 EM78P156NP EM78P156NM 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 17 18 TCC VDDVss P50 P51 P53 P60/INT P61 P62 P63 P64 P52 /RESET OSCI OSCO P67 P66 P65 EM78P156NAS 1 2 3 4 5 6 7 8 9 16 15 14 13 12 1110 17 18 NC NC 20 19 TCC VDDVss P50 P51 P53 P60/INT P61 P62 P63 P64 P52 /RESET OSCI OSCO P67 P66 P65 EM78P156NKM 1 2 3 4 5 6 7 8 9 16 15 14 13 12 1110 17 18 20 19 Vss VDD Fig. 1 Pin Assignment Table 1 EM78P156NP and EM78P156NM Pin Description Symbol Pin No. Type Function VDD 14 - * Power
ELANsat Tech EM78P156N, EM78P156N OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name X X X X X EXIF ICIF TCIF Power-On U U U U U 0 0 0 /RESET and WDT U U U U U 0 0 0 0x0F RF(ISR) Wake-Up from Pin Change U U U U U P P P Bit Name - - - - - - - - Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 0x0A IOCA Wake-Up from Pin Change P P P P P P P P Bit Name /PD7 /PD6 /PD5 /PD4 X /PD2 /PD1 /PD0 Power-On 1 1 1 1 U 1 1 1 /RESET and WDT 1 1 1 1 U 1 1 1 0x0B IOCB Wake-Up from Pin Change P P P P U P P P Bit Name OD7 OD6 OD5 OD4
ELANsat Tech EM78P156N, EM78P156N OTP ROM 18-Lead Plastic Small Outline (SOP) 300 mil This specification is subject to change without prior notice. 54 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100
EM78P156N OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Change Power on reset content 07/01/2003 1.2 Add the Device Characteristic at section 6.3 07/29/2004 Application Note AN-001 EM78P156N v.s. EM78P156E on the DC Characteristics This specification is subject to change without prior notice. 2
ELANsat Tech EM78P156N, EM78P156N OTP ROM EM78P156N 8-BIT MICRO-CONTROLLER Version 1.2 WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW
EM78P156N OTP ROM EM78P156N-G HXT V-I Fig. 36 Operating current range (based on high Freq. @ =25 ) vs. Voltage EM78P156N-G LXT V-I Fig. 37 Operating current range (based on high Freq. @ =25 ) vs. Voltage This specification is subject to change without prior notice. 51 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW
ELANsat Tech EM78P156N, EM78P156N OTP ROM EM78P156N-J HXT V-I Fig. 34 Operating current range (based on high Freq. @ =25 ) vs. Voltage EM78P156N-J LXT V-I Fig. 35 Operating current range (based on low Freq. @ =25 ) vs. Voltage This specification is subject to change without prior notice. 50 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW
ELANsat Tech EM78P156N, EM78P156N OTP ROM 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P, listed in Table 4 are used to check how the processor wakes up. Table 5 shows the events that may affect the status of T and P. Table 6 The Values of RST, T and P after RESET Reset Type T P Power on 1 1 /RESET during Operating mode *P *P /RESET wake-up during SLEEP mode 1 0 WDT during Operating mode 0 *P WDT wake-up during SLEEP mode 0 0 Wake-Up on pin change during SLEEP mode 1 0 *P: Previou
ELANsat Tech EM78P156N, EM78P156N OTP ROM Vth (Input thershold voltage) of I/O pins Max(-40 to 85 ) Typ 25 Min(-40 to 85 ) Fig. 18 Vth (Threshold voltage) of Port5 vs. VDD This specification is subject to change without prior notice. 41 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM
ELANsat Tech EM78P156N, EM78P156N OTP ROM R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in enable state, P50~P51 must be programmed as input pins. Under R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b), and Figure 8. PCWR
EM78P156N OTP ROM 6.2 AC Electrical Characteristic (Ta=25 °C, VDD=5V±5%, VSS=0V) Symbol Parameter Conditions Min Typ Max Unit Dclk Input CLK duty cycle 45 50 55 % Crystal type 100 DC ns Tins Instruction cycle time (CLKS="0") RC type 500 DC ns Ttcc TCC input period (Tins+20)/N* ns Tdrh Device reset hold time
ELANsat Tech EM78P156N, EM78P156N OTP ROM Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 input status changed Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT 1 (using very carefully) 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1) 3. Execute "ENI" or "DISI" 4. IF Port 6 change (interrupt) 4. Enable interrupt (Set IOCF.1) → Interrupt vector (
ELANsat Tech EM78P156N, EM78P156N OTP ROM PCRD PCWR PDWR PDRD TIN IOD P61~P67 PORT 0 1 M U X CLK CLK CLK P P P L L L R R R C C C D D D Q Q Q Q Q Q _ _ _ NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67 /SLEP T17 T10 T11 IOCE.1 Interrupt ENI Instruction DISI Instruction Interrupt (Wake-up from SLEEP) Next Instruction (Wake-up from SLEEP) CLK CLK CLK Q Q Q Q Q Q _ _ _ D D D P P P L L L R R R C C C RE.1 Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up This specification is subject to change without prior notice. 18 07.29.2004 (V1.
ELANsat Tech EM78P156N, EM78P156N OTP ROM Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency C1(pF) C2(pF) 455 kHz 100~150 100~150 2.0 MHz 20~40 20~40 Ceramic Resonators HXT 4.0 MHz 10~30 10~30 32.768kHz 25 15 100KHz 25 25 LXT 200KHz 25 25 455KHz 20~40 20~150 1.0MHz 15~30 15~30 2.0MHz 15 15 Crystal Oscillator HXT 4.0MHz 15 15 <Note> 1. The value of capacitors (C1, C2) is for reference. 3. External RC Oscillator Mode For some applications that do not need a very precise timing calculation, the RC os
ELANsat Tech EM78P156N, EM78P156N OTP ROM 4.5 RESET and Wake-up 1. RESET A RESET is initiated by one of the following events- (1) Power on reset. (2) /RESET pin input "low", or (3) WDT time-out (if enabled). The device is kept in a RESET condition for a period of approx. 18ms 1 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig.9. • The oscillator is running, or will be started. • The Program Counter (R2) is set to all "0". �
ELANsat Tech EM78P156N, EM78P156N OTP ROM Package Information 18-Lead Plastic Dual in line (PDIP) 300 mil This specification is subject to change without prior notice. 53 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW W
ELANsat Tech EM78P156N, EM78P156N OTP ROM Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as follows: ISB1: VDD=5V, WDT disable ISB2: VDD=5V, WDT enable Typical ISB1 and ISB2 vs. Temperature Temperature ( ) Current (uA) T yp ISB2 T yp ISB1 Fig. 30 Typical standby current (ISB1 and ISB2) vs. Temperature Maximum ISB1 and ISB2 vs. Temperature Temperature ( ) Current (uA) Max ISB2 Max ISB1 Fig. 31 Maximum standby current (ISB1 and ISB2) vs. Temperature This specification is subject to change without prior notice. 48 07.29.2004 (V
EM78P156N OTP ROM Table 9 The Summary of Maximum Operating Speeds Conditions VDD Fxt max.(MHz) 3.0 8.0 Two cycles with two clocks 5.0 20.0 2. Crystal Oscillator/Ceramic Resonators (XTAL) EM78P156N can be driven by an external clock signal through the OSCI pin as shown in Fig. 11 below. OSCI OSCO EM78P156N Ext. Clock Fig. 11 Circuit for Ext
ELANsat Tech EM78P156N, EM78P156N OTP ROM 0 1 1 Enable 1 0 0 Enable 1 0 1 Enable 1 1 0 Enable 1 1 1 Disable 2. Customer ID Register (Word 1) Bit 12~Bit 0 XXXXXXXXXXXXX • Bit 12~0: Customer’s ID code 4.9 Power On Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its steady state. EM78156N POR voltage range is 1.2V~1.8V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78156E will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very
ELANsat Tech EM78P156N, EM78P156N OTP ROM Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, user must connect the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8. • Bits 0~3,5 Not used. 9. IOCF (Interrupt Mask Register) 7 6 5 4 3 2
ELANsat Tech EM78P156N, EM78P156N OTP ROM • CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) • "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. • Only the lower 4 bits of IOC5 can be defined. • IOC5 and IOC6 registers are both readable and writable. 4. IOCA (Prescaler Counter Register) • IOCA register is readable. • The value of IOCA is equal to the contents of Prescaler counter. • Down counter. 5. IOCB (Pull-down Control Register) 7 6 5 4 3 2 1 0 /PD7 /PD6 /PD5 /PD4 - /PD2 /PD1 /PD0 • Bit 0
ELANsat Tech EM78P156N, EM78P156N OTP ROM vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-up. If DISI is executed before SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up. Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is, [a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be disabled. by software. However, the WDT bit in the option register remains enabled. Hence, the EM78P156N can be awakened only by Case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 Input
ELANsat Tech EM78P156N, EM78P156N OTP ROM Fig. 32 Operating voltage in temperature range from 0 to 70 Fig. 33 Operating voltage in temperature range from -40 to 85 This specification is subject to change without prior notice. 49 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW
EM78P156N OTP ROM • Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. • Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin. • Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin. • IOCC Register is both readable and writable. 7. IOCD (Pull-high Control Register) 7 6 5 4 3 2 1 0 /PH7 /PH6 /PH5 /PH4 /PH3
ELANsat Tech EM78P156N, EM78P156N OTP ROM 4.13 Timing Diagrams RESET Timing (CLK="0") CLK /RESET NOP Instruction 1 Executed Tdrh TCC Input Timing (CLKS="0") CLK TCC Ttcc Tins AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0". AC Test Input/Output Waveform 2.4 0.4 2.0 0.8 TEST POINTS 2.0 0.8 This specification is subject to change without prior notice. 36 07.29.2004 (V1.2) WWW.1
EM78P156N OTP ROM 4. FUNCTION DESCRIPTION Interrupt Controller ROM Instruction Register Instruction Decoder R2 ALU Stack ACC R3 R4 Oscillator/Timing Control WDT timer Prescaler R1(TCC) RAM DATA & CONTROL BUS OSCI OSCO /RESET TCC /INT I/O PORT 6 IOC6 R6 P60//INT P61 P62 P63 P64 P65 P66 P67 I/O PORT 5 IOC5 R5 P50 P51 P52 P53 IOCA Fig. 2 Function Block Diagram 4.1 Operational Reg
ELANsat Tech EM78P156N, EM78P156N OTP ROM 6.3 Device Characteristic The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristic illustrated herein are not guaranteed for it accuracy. In some graphs, the data maybe out of the specified warranted operating range. Vih/Vil (Input pins with schmitt inverter) Vih max (-40 to 85 ) Vih typ 25 Vih min (-40 to 85 ) Vil max (-40 to 85 ) Vil typ 25 Vil min (-40 to 85 ) Fig. 17 Vih, Vil of Port6 vs.
ELANsat Tech EM78P156N, EM78P156N OTP ROM * 20 pin SSOP 209mil : EM78P156NKM • 99.9% single instruction cycle commands • The transient point of system frequency between HXT and LXT is around 400KHz This specification is subject to change without prior notice. 5 07.29.2004 (V1.2) WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW
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