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Texas Instruments PCI7621 Data Manual

Texas Instruments PCI7621 Manual Online:

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Texas Instruments PCI7621 User Manual
Texas Instruments PCI7621 User Guide
Texas Instruments PCI7621 Online Manual

Text of Texas Instruments PCI7621 User Guide:

  • 8−32 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in thi

  • 5−9 5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the co

  • Texas Instruments PCI7621, 4−1 4 PC Card Controller Programming Model This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by § in Table 4−2. Any bit followed by a † is not cleared by the assertion

  • 8−35 8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit c

  • Texas Instruments PCI7621, 8−15 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Self-ID count Type RU R R R R R R R RU RU RU RU RU RU RU RU Default X 0 0 0 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Self-ID count Type R R R R R RU RU

  • Texas Instruments PCI7621, 2−11 Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 W13 A_A5 B06 A_INPACK E07 B_CE1 M18 AD1 N11 A_A6 G09 A_IORD C11 B_CE2 L19 AD2 U12 A_A7 B07 A_IOWR E11 B_D0 C16 AD3 V12 A_A8 B10 A_OE C12 B_D1 B16 AD4 W12 A_A9 G11 A_READY(IREQ) C04 B_D2 A15 AD5 R11 A_A10 A12 A_REG C05 B_D3 P19 AD6 U11 A_A11 B11 A_RESET A06 B_D4 P17 AD7 V11 A_A12 F09 A_USB_EN E02 B_D5 M13 AD8 N10 A_A13 G10 A_VS1 A03 B_D6 N18 AD9 R10 A_A14 F10 A_VS2 E08 B_D7 M15 AD10 U10 A_A15 B08 A_WAIT B03 B_D8 A17 AD11 V10 A_A

  • Texas Instruments PCI7621, 7−20 Table 7−23. GPIO Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 12 GPIO_ENB1 R/W GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for GPIO1. 0 = High-impedance output (default) 1 = Output is enabled 11−9 RSVD R Reserved. Bits 11−9 return 0s when read. 8 GPIO_DATA1 R/W GPIO1 data. When bit 15 (DISABLE_LPS) is set to 1 and GPIO1 output is enabled, the value written to this bit represents the logical data driven to the GPIO1 terminal. 7 DISABLE_BMC R/W Disable bus manager contender (BMC). This bit configures this terminal as bus manager contender or GPIO0. 0 = BMC (default) 1 = GPIO0 6 RSV

  • Texas Instruments PCI7621, 8−24 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the correspond

  • Texas Instruments PCI7621, 3−23 3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity. NOTE: T

  • Texas Instruments PCI7621, 8−16 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 8−13 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Isochronous receive channel mask high Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9

  • Texas Instruments PCI7621, 12−11 12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 12−12 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Capability ID and next item pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Capability ID and next item pointer Offset: 80h Type: Read-only Default: 0001h Table 12−12. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TY

  • Texas Instruments PCI7621, xi Section Title Page 14 Electrical Characteristics 14−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges 14−1. 14.2 Recommended Operating Conditions 14−1. . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Electrical Characteristics Over Recommended Operating Conditions 14−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions 14−5.

  • Texas Instruments PCI7621, 5−8 5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: ExCA interrupt and general control Offset: CardBus Socket Address + 803h: Card A ExCA Offset 03h Card B ExCA Offset 43h Type: Read/Write Default: 00h Table 5−6. ExCA Interrupt and General Control Register Description BIT SIGNAL TYPE FUNC

  • Texas Instruments PCI7621, 4−23 4.32 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can be programmed to generate general-purpose event signaling through GPE . See Table 4−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose event status Type RCU RCU R RCU RCU RCU RCU RCU Default 0 0 0 0 0 0 0 0 Register: General-purpose event status Offset: 88h Type: Read/Clear/Update, Read-only Default: 00h Table 4−10. General-Purpose

  • Texas Instruments PCI7621, 11−3 11.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11−2 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R RW R RW R RW R RW R RW RW R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Command Offset: 04h Type: Read/Write, Read-only Default: 0000h Table 11−2. Command Register Description BIT FIELD NAME TYPE DESCRIPTION 15−11 RSVD R Reserved. Bits 15−11 return 0s when read. 10 INT_DISABLE RW INT

  • Texas Instruments PCI7621, 12−8 12.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem identification Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem identification Offset: 2Eh Type: Read/Update Default: 0000h 12.11 Capabilities Pointer Register The

  • 4−24 4.33 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose event enable Type RW RW R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: General-purpose event enable Offset: 89h Type: Read-o

  • Texas Instruments PCI7621, 7−16 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI miscellaneous configuration Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI miscellaneous configuration Type RW R RW R RW RW RW RW R R R RW RW RW RW RW Default 0 0

  • Texas Instruments PCI7621, 11−10 11.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 11−11 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Capability ID and next item pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Capability ID and next item pointer Offset: 44h Type: Read-only Defa

  • Texas Instruments PCI7621, 4−36 4.49 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. On byte reads, the byte address is programmed into the serial bus index register, this register must be prog

  • Texas Instruments PCI7621, 3−10 PCI7x21/ PCI7x11 Current Limiting R ≈ 150 Ω Socket A LED MFUNCx Current Limiting R ≈ 150 Ω Socket B LED MFUNCy Figure 3−6. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during

  • 7−3 7.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R RW R RW R RW R

  • Texas Instruments PCI7621, 4−18 4.29 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type RW RW RW RW RW RW RW RW R RW RW RW R R R R Default 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type RW R

  • Texas Instruments PCI7621, 10−5 Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. Fault 1 RW Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending p

  • Texas Instruments PCI7621, vii Section Title Page 7 OHCI Controller Programming Model 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Command Register 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Status Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Class Code and Revision ID Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Latency

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