Quatech MPAC-100 Operation & User’s Manual

Text of Quatech MPAC-100 User Guide:

• MPAC-100 RS-232 PCI SYNCHRONOUS ADAPTER for PCI Card Standard compatible machines User's Manual QUATECH, INC. TEL: (330) 434-3154 662 Wolf Ledges Parkway FAX: (330) 434-1409 Akron, Ohio 44311 www.quatech.com

• Quatech MPAC-100, 13 FIFO Status Register The FIFO Status Register is used to return current status information about the internal FIFOs. The address of this read-only register is Base+9. Table 12 details the bit definitions of the register. This register can be ignored if the internal FIFOs are not being used. TXETXHTXF0RXERXHRXF0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 12 --- FIFO Status Register - Read Only Bit 7: Reserved, always 0. Bit 6: RXF --- Receive FIFO Full: This bit is set (logic 1) when the internal receive FIFO is completely full. The FIFO will accept no

• Quatech MPAC-100, 6 Addressing The MPAC-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAC-100 will occupy address locations 300 hex to 30F hex. If the computer in which the MPAC-100 is installed is running PCI Card and Socket Services, the base address is set by the client driver. If PCI Card and Socket Services are not being used, the base address is set by the MPAC-100 enabler program. The first four bytes of address space on the MPAC-100 contain t

• Quatech MPAC-100, 9.3.1 Using channel A for both transmit and receive This is the mode in which most applications will run. Set RXSRC (bit 1) in the Configuration Register to logic 0. This will configure the MPAC-100 to use W/REQA for receive DMA and DTR/REQA for transmit DMA. In addition to any other desired SCC configuration, ensure that the following bits are set according to Table 6: Set DTR/REQA for W/REQA timing. 1 4 Assert transmit DMA request when entry location of internal FIFO is empty. 05 WR7A' Enable WR7A' . 1 0 WR15A Enable DMA request-on-transmit on DTR/REQA. 12WR14A Disable transmit interrupts.01 Enable rec

• Quatech MPAC-100, 14 FIFO Control Register The FIFO Control Register is used to control the internal data FIFOs. The address of this register is Base+A (hex). Table 13 details the bit definitions of the register. This register can be ignored if the internal FIFOs are not being used. TX_RESET000RX_RESETEN_TOEN_PAT0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 13 --- FIFO Control Register - Read/Write Bit 7: Reserved, always 0. Bit 6: EN_PAT --- Enable Receive Pattern Detection: Set this bit (logic 1), to enable the receive pattern detection circuitry. Clea

• Quatech MPAC-100, 11 Configuration Register The Configuration Register is used to set the interrupt source and enable the interface between the SCC and the internal FIFOs. The address of this register is Base+5. Table 10 details the bit definitions of the register. 0RXSRCFIFOEN0INTS0INTS101 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 10 --- Configuration Register - Read/Write Bit 7: Internal Data FIFOs Present --- Reserved, always 1. This bit can be used as an indicator that internal data FIFOs are present. Other MPA-series products that are n

• Quatech MPAC-100, 8 SCC General Information The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAC-100 provides a single channel for communications, however, portions of the second channel can be utilized to support some special circumstances. The SCC can be configured to satisfy a wide variety of serial communications applications. Some of its protocol capabilities include: SDLC/HDLC (Bit Synchronous) Communications  Abort sequence generation and checking  Automatic zero

• Quatech MPAC-100, 10 Communications Register The Communications Register is used to set options pertaining to the clocks. The source and type of clock to be transmitted or received can be specified. External synchronization and RS-232 DTE test modes and can also be controlled with this register. The address of the Communications Register is Base+4. Table 9 details its bit definitions. 00TCKENRCKEN RLEN or SW_SYNC LLENEXTSYNCTM ST Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 9 --- Communications Register - Read/Write Bit 7: TM ST --- Test Mode Status: This bit can be used to read the status of the Test Mode

• Quatech MPAC-100, 9.6 Receive pattern detection The internal FIFOs are most useful in bit-synchronous operational modes because the SCC can generate a Special Condition interrupt when the closing flag of a bit-synchronous frame is received. This allows the SCC to run with per-character receive interrupts disabled while DMA transfers occur between the SCC and internal FIFOs. Byte-synchronous modes such as bisync, however, do not benefit from such a hardware assist for detecting the end-of-frame condition. On the contrary, with byte-oriented protocols it is usually necessary to check each byte received against a table of special function codes (e.g. SYNC, PAD, SDI, STX, EDI, ETX, etc.) to

• Quatech MPAC-100, Bit 1: RXSRC --- Receive FIFO DMA Source: This bit determines which SCC pins are used to control transmit and receive DMA transactions between the SCC and the internal FIFOs (when enabled). The transmit data FIFO is always used with SCC channel A. The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0, or with SCC channel B by setting RXSRC to logic 1. (See page 29 for information on using channel B.) W/REQADTR/REQA Transmit DMA W/REQBW/REQA Receive DMA RXSRC = 1 RXSRC = 0 Bit 0: Reserved, always 0. Quatech MPAC-100 User's Manual 39

• 19 DTE Interface Signals CIRCUIT AB - SIGNAL GROUND  CONNECTOR NOTATION: DGND  DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground. CIRCUIT BA - TRANSMITTED DATA  CONNECTOR NOTATION: TXD  DIRECTION: To DCE This signal transfers the data generated by the DTE through the communication channel to one or more remote DCE d

• Quatech MPAC-100, CIRCUIT DB - TRANSMIT SIGNAL ELEMENT TIMING (DCE SOURCE)  CONNECTOR NOTATION:TXCLK (DCE)  DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE. The DCE can use this information for its received data. CIRCUIT DD - RECEIVER SIGNAL ELEMENT TIMING (DCE SOURCE)  CONNECTOR NOTATION: RXCLK (DCE)  DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted by the DCE. The DTE can use this information for its received data. CIRCUIT LL - LO

• Quatech MPAC-100, and I/O regions, etc. Pressing the "N" key will show similar information for all non-Quatech PCI devices in the system, including those devices integrated on the motherboard. In this example, the "Base addr 0" resource is reserved. For users interested in even more details, PCI BIOS information can be displayed by pressing the "B" key. Pressing the "I" key displays the PCI interrupt routing table. Q - Quatech PCI adapters N - Other PCI devices X - EXIT M - Change to Basic Mode Quatech PCI Configuration Information Display Software

• Quatech MPAC-100, The QTPCI program is capable only of displaying the PCI configuration. It cannot be used to make changes. Q - Quatech PCI adapters N - Other PCI devices X - EXIT M - Change to Expert Mode Quatech PCI Configuration Information Display Software Version 1.03 INSTRUCTIONS: ------------------------ Press keys listed in the menu at the bottom of the screen. This program only displays information. It cannot make changes. PCI BIOS detected, version 2.10 Quatech PCI adapters detected -----------------------

• Quatech MPAC-100, 9.7 Receive FIFO timeout With asynchronous operational modes, the same problem exists. Namely, how is one to determine when a reception is complete? While the receive pattern detection may be useful here, the MPAC-100 also offers a timeout feature on the internal receive FIFO. If the internal FIFO is not empty and a time interval equal to a specified number of character-times has elapsed without any further data being received, a receive FIFO interrupt is generated and RX_FIFO bit in the Interrupt Status Register (see page 43) is set. A character-time is approximated

• Quatech MPAC-100, N/C N/C RxCLK (DTE) SYNCA N/C CD DGND DSR CTS RTS RxD TxD CGND 13 12 11 10 9 8 7 6 5 4 3 2 1 25 24 23 22 21 20 19 18 17 16 15 14 TM (OUTPUT) TxCLK (DTE) N/C N/C RLBK (OUTPUT) DTR N/C LLBK (OUTPUT) RxCLK (DCE) N/C TxCLK (DCE) RING Figure 2 --- MPAC-100 Output Connector The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback (RL). These signals are asserted with certain bits in the Communications Register. When a Test Mode (TM) condition is received from the DCE, an interrupt can optionally be generated. 18.1 5V fuse (pin 9) Pin 9 will have a 5volt fuse tied to VDD on the other end. This is compatible with

• Quatech MPAC-100, 8.4 Support for SCC Channel B The MPAC-100 is a single-channel device. Portions of SCC channel B are used to augment channel A. Channel B cannot be used for transmit, but may be used for receive, subject to certain limitations. 8.4.1 Receive data and clock signals The receive data signals RXDA and RXDB are tied together. The receive clock input signals RTxCA and RTxCB are also tied together. This can be useful in unusual applications. It would be possible to run the receiver and transmitter at different baud rates, using channel B's baud rate generator and receiver for the received data. Of course, the channel A transmitter and receiver can be run at diff

• Quatech MPAC-100, Copyright 2000 Quatech, Inc. NOTICE The information contained in this document is protected by copyright, and cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document are protected by copyright and can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice. The authors have taken due care in the preparation o

• Quatech MPAC-100, 3.2 Viewing Resources with Device Manager The following instructions provide step-by-step instructions on viewing resources used by the MPAC-100 in Windows 95/98 using the "Device Manager" utility. 1. Double click the "System" icon inside the Control Panel folder. This opens up the System Properties box. 2. Click the "Device Manager" tab located along the top of the System Properties box. 3. Double click the device group "Synchronous_Communication". The MPAC-100 model name should appear in the list of adapters. 4. Double click the MPAC-100 model name and a properties box should open for the hardware adapter. Quatech MPAC-100 User's Manual

• 1 Introduction The Quatech MPAC-100 is a PCI Type card and is PCI PC Card Standard Specification compliant. It provides a single-channel RS-232 synchronous communication port. The base address and IRQ are configured through the PCI hardware and software using utility programs provided by Quatech. There are no switches or jumpers to set. The MPAC-100 uses a Zilog 85230-compatible Serial Co

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