Hitachi SH7750 Hardware Manual

Text of Hitachi SH7750 User Guide:

• Hitachi SH7750, Rev. 6.0, 07/02, page 839 of 986 Notes: 1. Connect V DD-PLL1/2 , V DD-RTC , and V DD-CPG to V DDQ , and V SS-CPG , V SS-PLL1/2 , and V SSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for V IH min = V DDQ – 0.5 V and V IL max = 0.5 V with all output pins unloaded. 3. I DDQ is the sum of the V DDQ , V DD-PLL1/2 , V DD-RTC , and V DD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned

• Hitachi SH7750, Rev. 6.0, 07/02, page 154 of 986 (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. FPU_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000120; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; }

• Hitachi SH7750, Rev. 6.0, 07/02, page 933 of 986 TDI TMS TCK TDO t TCKcyc t TDO t TDIH t TDIS Figure 22.69 H-UDI Data Transfer Timing t PINBRK Figure 22.70 Pin Break Timing t NMIH t NMIL NMI Figure 22.71 NMI Input Timing

• Hitachi SH7750, Rev. 6.0, 07/02, page 684 of 986 16.2.12 Line Status Register (SCLSR2) Bit: 15 14 13 12 11 10 9 8 ———————— Initial value:00000000 R/W:RRRRRRRR Bit:76543210 ———————ORER Initial value:00000000 R/W:RRRRRRR(R/W)* Note: * Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER Description 0 Reception in progress, or reception has ended normally * 1 (Initial value) [Clearing conditions] • Po

• Hitachi SH7750, Rev. 6.0, 07/02, page 522 of 986 CKIO A26–A0 D63–D0 DACK Transfer from external memory space to external memory space Transfer source address Transfer destination address Data read cycle (1st cycle) Data write cycle (2nd cycle) Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0– CHCR3. Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each

• Hitachi SH7750, Rev. 6.0, 07/02, page 2 of 986 Table 1.1 SH7750 Series Features (cont) Item Features CPU • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers • RISC-type instruction set (upward-compatible with SH Series)  Fixed 16-bit instruction length for improved code efficiency  Load-store architecture  Delayed branch instructi

• Hitachi SH7750, Rev. 6.0, 07/02, page 964 of 986 (10) BUS 32 (64M: 1M × 16b × 4) × 2 * AMX 2 64M, column-addr-8bit 16MB SH7750 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used

• Hitachi SH7750, Rev. 6.0, 07/02, page 617 of 986 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) Pφ φφ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 31250 0 14 –1.70 0 15

• Hitachi SH7750, Rev. 6.0, 07/02, page 821 of 986 Item Symbol Min Typ Max Unit Test Conditions V OH 2.4——VOutput voltage All output pins V OL ——0.55 Pull-up resistance All pull-up resistance R pull 20 60 180 kΩ Pin capacitance All pins C L ——10pF Notes: 1. Connect V DD-PLL1/2 , V DD-RTC , and V DD-CPG to V DDQ , and V SS-CPG , V SS-PLL1/2 , and V SSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for V IH min = V DDQ – 0.5 V and V IL max = 0.5 V with all output pins unloaded. 3. I DDQ is the su

• Hitachi SH7750, Rev. 6.0, 07/02, page 216 of 986 Table 8.3 Execution Cycles (cont) Lock Functional Category No. Instruction Instruc- tion Group Issue Rate Latency Execu- tion Pattern Stage Start Cycles 151 STC GBR,Rn CO 2 2 #20 — — — 152 STC Rp_BANK,Rn CO 2 2 #20 — — — 153 STC SR,Rn CO 2 2 #20 — — — 154 STC SSR,Rn CO 2 2 #20 — — — 155 STC SPC,Rn CO 2 2 #20 — — — 156 STC VBR,Rn CO 2 2 #20 — — — 157 STC.L DBR,@-Rn CO 2 2/2 #22 — — — 158 STC.L SGR,@-Rn CO 3 3/3 #23 — — — 159 STC.L GBR,@-Rn CO 2 2/2 #22 — — — 160 STC.L Rp_BANK,@-Rn CO 2 2/2 #22 — — — 161 STC.L SR,@-Rn CO 2 2/

• Hitachi SH7750, Rev. 6.0, 07/02, page 235 of 986 9.7 Hardware Standby Mode (SH7750S, SH7750R Only) 9.7.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1. Interrupts and manual resets are not available; 2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up resistance is off. 3. Even when no power is supplied to power pins other t

• Hitachi SH7750, Rev. 6.0, 07/02, page l of I Table 22.20 Clock Timing (HD6417750RF200)................................................................... 842 Table 22.21 Clock Timing (HD6417750SF200) ................................................................... 842 Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)........................................................................................... 843 Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133)........................... 843 Table 22.24 Clock Timing (HD6417750VF128).........................

• Rev. 6.0, 07/02, page 769 of 986 Program execution state No No Yes No Yes No Yes Yes No No Yes Yes No Yes No No Yes No Yes Save SR to SSR; save PC to SPC Set interrupt source in INTEVT Set BL, MD, RB bits in SR to 1 Branch to exception handler Interrupt generated? (BL bit in SR = 0) or (sleep or standby mode)? NMI? Level 14 interrupt? Level 1 interrupt? I3�

• Rev. 6.0, 07/02, page 468 of 986 Tm1 CKIO A / RD/ D31–D0 Tmd1w Tmd1w Tmd1 Tmd2 DACKn (DA) D0 D1 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.68 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes)

• Hitachi SH7750, Rev. 6.0, 07/02, page 970 of 986 (16) BUS 32 (64M: 1M × 32b × 2) × 1 * AMX 5 64M, column-addr-8bit 8MB SH7750 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used

• Hitachi SH7750, Rev. 6.0, 07/02, page 718 of 986 17.3.6 Data Transmit/Receive Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set

• Hitachi SH7750, Rev. 6.0, 07/02, page 959 of 986 (5) BUS 64 (16M: 1M × 8b × 2) × 8 * AMX 1 AMXEXT 0 16M, column-addr-9bit 16MB SH7750 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A23 A23 A11 BANK selects bank address A13 A22 H/L A10 Address precharge setting A12 A21 0 A9 A11 A20 A11 A8 A10 A19 A10 A7 A9 A18 A9 A6 A8 A17 A8 A5 A7 A16 A7 A4 A6 A15 A6 A3 A5 A14 A5 A2 A4 A13 A4 A1 A3 A12 A3 A0 Address A2 Not used A1 Not used A0 Not used

• Hitachi SH7750, Rev. 6.0, 07/02, page 121 of 986 The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specific

• Rev. 6.0, 07/02, page 305 of 986 1 2 Operation selection Select count clock Underflow interrupt generation setting When input capture function is used 3 4 5 6 Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is

• Hitachi SH7750, Rev. 6.0, 07/02, page 354 of 986 Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. Bit 30: MRSET Description 0 All-bank precharge (Initial value) 1 Mode register setting Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both enabled) Bit 29: TRC2 Bit 28: TRC1 Bit 27: TRC0 RAS Precharge Interval Immediately after Refresh 0000(Initial value) 13 106 19 10012 115 1018 121 Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written w

• Rev. 6.0, 07/02, page 976 of 986 (22) BUS 32 (16M: 256k × 32b × 2) × 1 * AMX 7 16M, column-addr-8bit 2MB SH7750 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H/L A9 Address precharge setting A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11

• Hitachi SH7750, Rev. 6.0, 07/02, page 307 of 986 • Operating on on-chip RTC output clock The on-chip RTC output clock can be selected as the timer clock in channels 0 to 2 by means of the TPSC2–TPSC0 bits in TCR. Figure 12.6 shows the timing in this case. N + 1 N N – 1 RTC output clock TCNT Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input mode. 2. Use bits TPSC2–TPSC0 in the timer control register (TCR) to set an internal clock or the on-

• Rev. 6.0, 07/02, page 554 of 986 CLK ID1, ID0 RAS, CAS, WE D63–D0 A25–A0 RA CA D0 D1 D2 D3 RD BA DTR 00 Figure 14.29 Single Address Mode/Burst Mode/External Bus → →→ → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer RA CA WT BA D0 D1 D2 D3 D5 D4DTR CLK ID1, ID0 RAS, CAS, WE D63–D0 A25–A0 Figure 14.30 Single Addr

• Hitachi SH7750, Rev. 6.0, 07/02, page 48 of 986 • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF4 XF8 XF12 XF1 XF5 XF9 XF13 XF2 XF6 XF10 XF14 XF3 XF7 XF11 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR

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