FSP Technology EP450 series Specifications

Text of FSP Technology EP450 series User Guide:

• FSP Technology EP450 series, Page 22 of 26 Rev. A 12 I nterface Circuit The interface circuit (refer to Figure S-10) USB communication, and plug & play for Windows 95/98/2000/XP/NT. Figure S-10 USB I nterface Circuit

• FSP Technology EP450 series, Page 15 of 26 Rev. A 7 Active Clamp The purpose of Clamp is to pull down the output voltage while two sets of Inverter MOSFET are OFF. The Clamp effect is active during the period of 0Vac at battery mode. CLAMP principle is shown in the last paragraph of Chapter 6 Inverter Operation.

• Page 16 of 26 Rev. A 8 Microprocessor(CPU) Control Circuit The CPU is supplied by +5Vdc power supply to pin7 with ground pin at pin3. An extra oscillation circuitry consisting of C01, C02, and crystal XL1 is connected to pin4 &5. The Vesta series is using MOTOROLA/MC68HC908JL8CSP CPU. The pin definition is listed below(Figure S-6): PI N FUNCTI ON Pin1 N/ A

• FSP Technology EP450 series, лчиттничюнльтцию. глтчн.Бзвыдны www.sotmarket.ru дбняинфмциятв, тзывы,бзыиы Инструкция для FSP EP-650 Перейти в карточку товара 8 800 775 98 98

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• Page 23 of 26 Rev. A 13 Troubleshooting WARNI NG 13.1 Troubleshooting can be done by qualified engineer or technician only. 13.2 Use isolated AC source for your oscilloscope to prevent floating voltage problem between UPS chassis ground and system reference ground. 13.3 Before opening the cover, turn off the main switch and unplug the input power cord. 13.4 Beca

• FSP Technology EP450 series, Page 11 of 26 Rev. A 5 Line and Zero-Crossing Detection Please refer Figure S-4 5.1 Line Detection The input voltage is fully rectified and generates a signal. The signal will be sent to pin 11 of CPU through a voltage divider at R45, R45A and R40//R47. By monitoring this rectified sinusoidal voltage, the CPU can identify if the utility is normal or abnormal. There are two methods to evaluate if line voltage is abnormal. 5.1.1 Waveform detection: If breakout occurs, the CPU is able to immediately detect it and transfers to battery mode. The waveform detection has a short response time. 5.1.2 RMS value dete

• FSP Technology EP450 series, Page 7 of 26 Rev. A 3 Control power circuit The control power (+12Vdc and + 5Vdc) comes from the following sources (Figure S-2). 3.1 Start without input AC power (Cold start): A “Cold start “is described as follows: 3.1.1 When “ON/OFF” switch (SW1) is pressed, a positive battery current flows through SW1 to charge C15. 3.1.2 Q12 base receives a HI pulse and turn on (signal bypass C15 at t=0, and charge C15 at t>0). 3.1.3 When Q12 turns on, the Q12 collector will drop to LOW and turn on Q11 (MPS2907A). 3.1.4 When Q11 turns on, the positive battery voltage via Q12 collector and establishes a + 12Vdc powe

• FSP Technology EP450 series, Page 6 of 26 Rev. A 2.6 CPU (MOTOROLA/ MC68HC908JL8CSP) The Central Process Unit 2.7 Electricity Switch It controls the + 5Vdc and +12Vdc supplies. +5Vdc and +12Vdc Control Power Generator. Provide +5Vdc (generated from 7805 regulator) and +12Vdc power supply. 2.8 Charger: The source for the Charger comes from the mains through the transformer and full-bridge inverter. The charger is controlled with high frequency technology and the acceptable charging voltage is 13.6~13.9V. 2.9 I nverter Circuit: The inv

• FSP Technology EP450 series, Page 4 of 26 Rev. A 1 I ntroduction EP series is a line interactive power system that has a step wave output. It prevents impulse, surge, sag and power outage situations. It provides the UPS output load with a reliable source. It has the following functions: 1.1 Boost: If the utility voltage drops to line boost activated point*, the AVR will be activated and increase the input voltage by 1.18 times of incoming utility voltage. * Boost activated point 110 VAC 120 VAC 220 VAC 230 VAC 240 VAC 99 VAC 108 VAC 198 VAC 207 VAC 216 VAC

• FSP Technology EP450 series, Page 3 of 26 Rev. A Table of Contents 1. I ntroduction……………………………………………………. 4 2. Block Diagram ……………………………………………....... 5 3. Control Power Circuit ……………………………………….. 7 4. Battery Charger ………………………………………………. 9 5. Line and Zero-Crossing Detection ……………………….. 11 6. I nverter Operation …………………………………………… 13 7. Active Clamp …………………………………………………… 15 8. Microprocessor (CPU) Control Circuit ………………...... 16 9. Relay Circuit ………………………�

• Page 13 of 26 Rev. A 6 I nverter Operation The Inverter circuit (Figure S-5) and PWM control are only active under Battery mode. The Inverter circuit of Vesta is based on a full-Bridge circuitry and its output is driven by a transistor which is controlled by CPU. Refer to the Inverter circuit diagram, the CPU.M1, CPU.M2, CPU.M3, and CPU.M4 signals are generated by CP

• FSP Technology EP450 series, Page 20 of 26 Rev. A 10 Displays, Audio Alarm and Control Button 10.1 Control button ON/OFF Button: Push it to turn on UPS, and push again to turn off UPS. (Please refer to Chapter 3 for cold start & AC start) 10.2 Audio alarm The buzzer is controlled by pin16 of CPU. When CPU sends a HI signal to buzzer from pin16, buzzer is beeping. And CPU sends LOW signal to stop buzzer. 10.3 Display (Figure S-8) There are 3 LEDs on front panel. While control button is turned on, CPU sends a HI signal to turn on LED. Figure S-8 Display Circuit

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