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Siemens SAK-C167CR-LM Manual 

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Siemens SAK-C167CR-LM User Manual
Siemens SAK-C167CR-LM User Guide
Siemens SAK-C167CR-LM Online Manual

Text of Siemens SAK-C167CR-LM User Guide:

  • Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 1 of 11 - Microcontroller Components Errata Sheet May 29, 1998 / Release 1.1 Device: SAK-C167CR-LM SAK-C167CR-L25M Stepping Code / Marking: ES-DB, DB Package: MQFP-144 This Errata Sheet describes the deviations from the current user documentation. The classification and numbering system is module oriented in a continual ascendin

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 2 of 11 - Functional Problems: PWRDN.1: Execution of PWRDN Instruction while pin NMI# = high When instruction PWRDN is executed while pin NMI# is at a high level, power down mode should not be entered, and the PWRDN instruction should be ignored. However, under the conditions described below, the PWRDN instruction may not be ignored, and no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This problem

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 3 of 11 - CPU.17: Arithmetic Overflow by DIVLU instruction For specific combinations of the values of the dividend (MDH,MDL) and divisor (Rn), the Overflow (V) flag in the PSW may not be set for unsigned divide operations, although an overflow occured. E.g.: MDH MDL Rn MDH MDL F0F0 0F0Fh : F0F0h = FFFF FFFFh, but no Overflow indicated ! (result with 32-bit precision: 1 0000h) The same malfunction appears for the following combinations: n0n0 0n0n : n0n0 n00n 0nn0 : n00n n000 000n : n000 n0nn 0nnn : n0nn where n means any Hex Dig

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 4 of 11 - ADC.11: Modifications of ADM field while bit ADST = 0 The A/D converter may unintentionally start one auto scan single conversion sequence when the following sequence of conditions is true: (1) the A/D converter has finished a fixed channel single or continuous conversion of an analog channel n > 0 (i.e. contents of ADCON.ADCH = n during this conversion) (2) the A/D converter is idle (i.e. ADBSY = 0) (3) then the conversion mode in the ADC Mode Selection field ADM is changed to Auto Scan

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 5 of 11 - X12: P0H spikes after XPER write access and external 8-bit Non-multiplexed bus When an external 8-bit non-multiplexed bus mode is selected and P0H is used for general purpose I/O, and an internal (byte or word) write access to an XBUS peripheral (e.g. XRAM, CAN, or I²C module) is performed, and an external bus cycle is directly following the internal XBUS write cycle, then P0H is actively driven with the write data for approx. 7ns (spikes on P0H). The spikes also occur if P0H is configured a

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 6 of 11 - Deviation from Electrical- and Timing Specification: The following table lists the deviations of the DC/AC characteristics from the specification in the C167CR-4RM Data Sheet 7.97 and C167SR/CR-L25M Data Sheet Addendum 1998-03 Problem Parameter Symbol Limit Values Unit Test short name min. max. Condition DCVOL.1 Output low voltage (Port0/1/4, ALE, RD#, WR#, WRH#/BHE, CLKOUT, RSTOUT#) V OL - 0.45 V I OL = 2.0 mA instead of 2.4 mA DCAH.1 ALE active c

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 7 of 11 - Parameter Symbol Max CPU = 20 Clock MHz Variable 1/2TCL = CPU Clock 1 to 20 MHz Unit min. max. min. max. WR#/WRH# low time (with RW-delay) t12 38+tc instead of 40+tc -2TCL-12+tc instead of 2TCL -10+tc -ns WR#/WRH# low time (no RW-delay) t13 63+tc instead of 65+tc -3TCL-12+tc instead of 3TCL -10+tc -ns ALE falling edge to CS# t38 -7-ta instead of - 4-ta 10-ta -7-ta instead of - 4-ta 10-ta ns RDCS#/WRCS# low time (with RW-delay) t48 38+tc instead of 40+tc -2TCL-12+tc instead of 2TCL -10+tc -ns RDCS#/WRCS# low time (with RW-delay) t49 63+tc instead of 65+tc -3TCL-12+tc instead of 3TCL -10+tc -ns Notes: 1

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 8 of 11 - ADCC.2: ADC Overload Current During exceptional conditions in the application system an overload current I OV can occur on the analog inputs of the A/D converter when V AIN > V dd or V AIN < V ss . For this case, the following conditions are specified in the Data Sheet: I OVmax = | ±5 mA | The specified total unadjusted error TUE max = | ±2 LSB | is only guaranteed if overload conditions occur on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. Due to an inte

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 9 of 11 - 6. Effects on the Conversion Result and TUE The effect on the conversion result and the TUE has to be calculated based on the current I ANx and the impedace of the analog source R ASRC . I ANn causes an external voltage U∆n at the analog channel ANn which is the reason for an additional unadjusted error AUE of the conversion result. This AUE can increase the specified total unadjusted error TUE (Specified value: TUE = ± 2 LSB). The voltage U∆n is nearly independent on the voltage value of the analog source. U∆n = I ANn * R ASRC AUE = U∆n / 1 LSB [U∆n in mV and LSB

  • Siemens SAK-C167CR-LM, Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 10 of 11 - History List (since device step BA) Functional Problems Functional Problem Short Description Fixed in step PWRDN.1 Execution of PWRDN Instruction while pin NMI# = high CPU.8 Jump instruction in EXTEND sequence CB CPU.9 PEC Transfers during instruction execution from Internal RAM CB CPU.11 Stack Underflow during Restart of Interrupted Multiply CB CPU.17 Arithmetic Overflow by DIVLU instruction RST.1 System Configuration via P0L.0 during Software/Watchdog Timer Reset CB RST.3 Bidirectional Hardware Reset DA ADC.8 CC31/ADC Interference CB ADC.10 Start of Standard Conversion at

  • Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 11 of 11 - In addition to the description in the C167 Derivatives User’s Manual V2.0, the following feature enhancements have been implemented in the C167CR-LM CB-step and all higher steps: Incremental position sensor interface For each of the GPT1 timers T2, T3, T4 of the GPT1 unit, an additional operating mod

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