Alpha Data ADM-PCIE-8K5-FH Operation & User’s Manual

Text of Alpha Data ADM-PCIE-8K5-FH User Guide:

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AG17 SFP+_TX_DISABLE 3.3 AE16 SFP+_TX_FAULT 3.3 AG7 SFP+_TX0_N MGT AG8 SFP+_TX0_P MGT AF5 SFP+_TX1_N MGT AF6 SFP+_TX1_P MGT AB5 SFP+_TX2_N MGT AB6 SFP+_TX2_P MGT AA3 SFP+_TX3_N MGT AA4 SFP+_TX3_P MGT AH19 SFP+0_MOD_ABS 3.3 AH18 SFP+0_SCL 3.3 AG16 SFP+0_SDA 3.3 AE18 SFP+1_MOD_ABS 3.3 AF18 SFP+1_SCL 3.3 AD16 SFP+1_SDA 3.3 AF17 SFP+2_MOD_ABS 3.3 AF19 SFP+2_SCL 3.3 AE17 SFP+2_SDA 3.3 AN17 SFP+3_MOD_ABS 3.3 AG19 SFP+3_SCL 3.3 AD18 SFP+3_SDA 3.3 AU30 S

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage N23 DDR4_0_DQ27 1.2 R22 DDR4_0_DQ28 1.2 P21 DDR4_0_DQ29 1.2 A18 DDR4_0_DQ3 1.2 R21 DDR4_0_DQ30 1.2 P20 DDR4_0_DQ31 1.2 E20 DDR4_0_DQ32 1.2 F18 DDR4_0_DQ33 1.2 F20 DDR4_0_DQ34 1.2 E18 DDR4_0_DQ35 1.2 F19 DDR4_0_DQ36 1.2 G20 DDR4_0_DQ37 1.2 H18 DDR4_0_DQ38 1.2 H17 DDR4_0_DQ39 1.2 A20 DDR4_0_DQ4 1.2 G22 DDR4_0_DQ40 1.2 E23 DDR4_0_DQ41 1.2 G21 DDR4_0_DQ42 1.2 F23 DDR4_0_DQ43 1.2 H24 DDR4_0_DQ44 1.2 E22 DDR4_0_DQ45 1.2 H23 DDR4_0_DQ46 1.2 E21 DDR4_0_DQ47 1.2 J23 DDR4_0_DQ48 1.2 K22 DDR4_0_DQ49 1.2 D18 DDR4_0_DQ5 1.2 K23 DDR4_0_DQ50 1.2 L24 DDR4_0_DQ51 1.2 J24 DDR4_0_DQ52 1.2 L20 DDR4_0_DQ53 1.2 L23 DDR4_0_DQ54 1.2

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.5 SFP+ Four SFP+ cages are available at the front panel. All cages are capable of housing either active optical or passive copper SFP compatible components. The communication interface can run at up to 16.375Gbps per channel. These cages are ideally suited for 10 Gigabit Ethernet or any other protocol supported by the Xilinx GTH Transceivers. Please see Xilinx User Guide UG576 for more details on the capabilities of the transceivers. Both SFP+ cages have control signals connected to the FPGA. Their connectivity is detailed in the Complete Pinout Table at the end of this document. The notation used in the pin assignments is SFP0 through SFP3 with locati

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual • set_property CONFIG_MODE {BPI16} [current_design] • set_property CFGBVS GND [ current_design ] • set_property CONFIG_VOLTAGE 1.8 [ current_design ] Generate an MCS file with these properties (write_cfgmem): • -format MCS • -size 128 • -interface BPIx16 • -loadbit "up 0x0000000 <directory/to/file/filename.bit>" (failsafe location) • -loadbit "up 0x2000000 <directory/to/file/filename.bit>" (default location) Program with vivado hardware manager with these settings: • BPI part number: mt28gu01gaax1e-bpi-x16 • State of non-config mem I/O pins: Pull-none • RS bits: 25

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AJ29 TE485 1.8 AT19 USER_LED_G0 3.3 AU19 USER_LED_G1 3.3 AU20 USER_LED_R 3.3 AV18 USR_SW 3.3 Table 14 : Complete Pinout Table Page 35Complete Pinout Table ad-ug-1342_v1_0.pdf

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.8 SMA Timing Input All cards are fitted with a U.FL connector that can be utilized as a timing input. This connector can be accessed with a U.FL cable internal to the chassis, or cabled to an SMA or similar connector at the front panel. Contact [email protected] for front panel connector options. Input is on FPGA pin AL30, IOSTANDARD LVCMOS18 The signal is isolated through a optical isolator part number ACPL-M61L with a 739 ohm of series resistance. Figure 10 : Timing Input Schematic 3.9 USB Front Panel Interface The ADM-PCIE-8K5-FH houses two USB ports. The upper connector connects to the system monitor system, while the lower connector allows program

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage D2 FIREFLY1_RX0_P MGT C3 FIREFLY1_RX1_N MGT C4 FIREFLY1_RX1_P MGT B1 FIREFLY1_RX2_N MGT B2 FIREFLY1_RX2_P MGT A3 FIREFLY1_RX3_N MGT A4 FIREFLY1_RX3_P MGT AJ16 FIREFLY1_SCL 3.3 AH16 FIREFLY1_SDA 3.3 AN16 FIREFLY1_SEL_L 3.3 D5 FIREFLY1_TX0_N MGT D6 FIREFLY1_TX0_P MGT C7 FIREFLY1_TX1_N MGT C8 FIREFLY1_TX1_P MGT B5 FIREFLY1_TX2_N MGT B6 FIREFLY1_TX2_P MGT A7 FIREFLY1_TX3_N MGT A8 FIREFLY1_TX3_P MGT AJ15 FLASH_A0 1.8 AK15 FLASH_A1 1.8 AN13

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.6 FireFly If the 8K5-FH is ordered with the XCKU115 FPGA, two optional FireFly receptacles near the front of the board allow for additional 16.375G lanes. The FireFly connections have the same capabilities as the SFP+ cages, with much greater lane width. There are 4 lanes per FireFly, adding up to 8 lanes at 16.375Gps resulting in 131Gbps total bandwidth. This can be configured in a ring orientation as depicted in the image below, or allow for MPO style breakouts at the front panel (full-height panel only).The ADM-PCIE-8K5-FH support both copper and optical FireFly modules. More information

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.1.2 LEDs There are 6 LEDs on the ADM-PCIE-8K5-FH, 3 of which are general purpose and whose meaning can be defined by the user. The other four have fixed functions described below: Figure 6 : LEDs Comp. Ref. Function ON State OFF State D4 DONE FPGA is configured FPGA is not configured D2 USER_LED_G0 User defined '0' pin AT19 User defined '1' pin AT19 D8 USER_LED_G1 User defined '0' pin AU19 User defined '1' pin AU19 D7 USER_LED_R User defined '0' pin AU20 User defined '1' pin AU20 D5 Status 0 See Status LED Definitions D6 Status 1 Se

• ADM-PCIE-8K5-FH User Manual 2 PCB Information 2.1 Physical Specifications The ADM-PCIE-8K5-FH complies with PCI Express CEM revision 3.0. Description Measure Total Dy 111 mm Total Dx (Inc. SFP+ Cages) 173 mm Total Dz 17.5 mm Weight 250g Table 1 : Mechanical Dimensions 2.2 Chassis Requirements 2.2.1 PCI Express The ADM-PCIE-8K5-FH is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes, using the

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Table 5 PCIe Reference Clocks ..................................................................................................................... 7 Table 6 Fabric Clock ....................................................................................................................................... 8 Table 7 EMCCLK ............................................................................................................................................ 8 Table 8 SFP+ Reference Clocks .................................................................................................................... 8 Table 9 FireFly Referen

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.12 User EEPROM A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part number M24C02-RMC6TG. The address pins A2, A1, and A0 are all strapped to a logical '0'. Write protect (WP), Serial Clock (SCL), and Serial Data (SDA) pin assignments can be found in Complete Pinout Table with the names SPARE_WP, SPARE_SCL, and SPARE_SDA respectively. WP, SDA, and SCL signals all have external pull-up resistors on the card. Page 19Functional Description ad-ug-1342_v1_0.pdf

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual series. Take care to supply a safe clock in on these signals. See Xilinx UG576 for more details acceptable on GTH reference clocks. SI5328_REFCLK_OUT1 comes from the onboard jitter attenuator which can feedback a recovered clock from the GTH channel for particular standards. The Jitter Attenuator is not fitted by default and requires a custom bulid option. Contact [email protected] for more details. Signal Target FPGA Input I/O Standard "P" pin "N" pin SI5328_REFCLK_OUT1 MGTREFCLK0_231 LVDS K10 K9 PCIE_REFCLK_1 MGTREFCLK1_231 LVDS H10 H9 GTH_CLK_2 MGTREFCLK0_232 LVDS F10 F9 EXT_CLK MGTREFCLK1_232 User D10 D9 Table 9 : FireFly Reference C

• ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AV5 PCIE_TX1_PIN_N MGT AV6 PCIE_TX1_PIN_P MGT AU7 PCIE_TX2_PIN_N MGT AU8 PCIE_TX2_PIN_P MGT AT5 PCIE_TX3_PIN_N MGT AT6 PCIE_TX3_PIN_P MGT AR7 PCIE_TX4_PIN_N MGT AR8 PCIE_TX4_PIN_P MGT AP5 PCIE_TX5_PIN_N MGT AP6 PCIE_TX5_PIN_P MGT AN7 PCIE_TX6_PIN_N MGT AN8 PCIE_TX6_PIN_P MGT AM5 PCIE_TX7_PIN_N MGT AM6 PCIE_TX7_P

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 2.3 Thermal Performance The ADM-PCIE-8K5-FH comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will clear the FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your application power and multiply by Theta JA from the table below, and add your systems internal ambient temperature. If you are using the fan provided with the board, you will fin

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AL29 GP1_1V8_P 1.8 (NC by default) AE7 GTH_CLK_0_PIN_N MGT_CLK AE8 GTH_CLK_0_PIN_P MGT_CLK AA7 GTH_CLK_1_PIN_N MGT_CLK AA8 GTH_CLK_1_PIN_P MGT_CLK F9 GTH_CLK_2_PIN_N MGT_CLK F10 GTH_CLK_2_PIN_P MGT_CLK AK31 H/F 1.8 R11 INIT_B_1V8 1.8 G15 MEM_CLK_0_PIN_N 1.2 (External Term Provided) G16 MEM_CLK_0_PIN_P 1.2 (External Term Provided) AN22 MEM_CLK_1_PIN_N 1.2 (External Term Provided) AM22 MEM_CLK_1_PIN_P 1.2 (External Term Provided) H9 PCIE_REFCLK_1_PIN_N MGT_CLK H10 PCIE_REFCLK_1_PIN_P MGT_CLK AT9 PCIE_REFCLK_2_PIN_N MGT_CLK AT10 PCIE_REFCLK_2_PIN_P MGT_CLK AW3 PCIE_RX0_N MGT AW4

• ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage E15 DDR4_0_C1 1.2 J13 DDR4_0_C2 1.2 K12 DDR4_0_CK_C 1.2 K13 DDR4_0_CK_T 1.2 E16 DDR4_0_CKE 1.2 D15 DDR4_0_CS_N 1.2 D19 DDR4_0_DM0 1.2 D24 DDR4_0_DM1 1.2 L17 DDR4_0_DM2 1.2 T23 DDR4_0_DM3 1.2 H19 DDR4_0_DM4 1.2 H21 DDR4_0_DM5 1.2 K21 DDR4_0_DM6 1.2 P19 DDR4_0_DM7 1.2 P13 DDR4_0_DM8 1.2 B20 DDR4_0_DQ0 1.2 C18 DD

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.7.2 System Monitor Status LEDs LEDs D6 (Red) and D5 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red (together) Attention - critical alarm active Flashing Green + Flashing Red (alternating) Service Mode Flashing Green + Red Attention - alarm active Red Missing application firmware or invalid firmware Flashing Red FPGA configuration cleared to protect board Table 13 : Status LED Definitions Page 14 Functional Description ad-ug-1342_v1_0.pdf

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual 3.2 Clocking The ADM-PCIE-8K5-FH provides reference clocks for the DDR4 SDRAM banks and the I/O interfaces available to the user. After a clock is programmed to a certain frequency, that frequency will become the default on power-up. Any clock out of an Si5338 Clock Synthesizer is re-configurable over I2C. This allows the user to configure almost any arbitrary clock frequencies during application run time. Please see the Alpha Data API functions for examples of how this is done. Note: use "set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]" to ensure the user design does not

• ADM-PCIE-8K5-FH User Manual Revision History Date Revision Changed By Nature of Change 16 Feb 2018 1.0 D. Flint Initial Release Address: 4 West Silvermills Lane, Edinburgh, EH3 5BD, UK Telephone: +44 131 558 2600 Fax: +44 131 558 2700 email: [email protected] website: http://www.alpha-data.com Address: 611 Corporate Circle Suite H Golden, CO 80401 Telephone: (303) 954 8768 Fax: (866)

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AV24 DDR4_1_DM0 1.2 AV28 DDR4_1_DM1 1.2 AK27 DDR4_1_DM2 1.2 AD25 DDR4_1_DM3 1.2 AR26 DDR4_1_DM4 1.2 G35 DDR4_1_DM5 1.2 K36 DDR4_1_DM6 1.2 E36 DDR4_1_DM7 1.2 F38 DDR4_1_DM8 1.2 AV23 DDR4_1_DQ0 1.2 AT22 DDR4_1_DQ1 1.2 AR28 DDR4_1_DQ10 1.2 AW25 DDR4_1_DQ11 1.2 AU27 DDR4_1_DQ12 1.2 AV26 DDR4_1_DQ13 1.2 AT28 DDR4_1_DQ14 1.2 AW26 DDR4_1_DQ15 1.2 AL28 DDR4_1_DQ16 1.2 AJ25 DDR4_1_DQ17 1.2 AH26 DDR4_1_DQ18 1.2 AH24 DDR4_1_DQ19 1.2 AT24 DDR4_1_DQ2 1.2 AJ26 DDR4_1_DQ20 1.2 AJ24 DDR4_1_DQ21 1.2 AL27 DDR4_1_DQ22 1.2 AK25 DDR4_1_DQ23 1.2 AD26 DDR4_1_DQ24 1.2 AG27 DDR4_1_DQ25 1.2 AE27 DDR4_1_DQ26 1.2 AF27 DDR4_1_DQ27

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2util-win-2.5.0.zip The USB driver install file is downloadable here: ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2_usb_inf.zip Use "avr2util.exe /?" to see all options. For example "avr2util.exe /usbcom com4 display-sensors" will display all sensor values. 3.10 Configuration There are two main ways of configuring the FPGA on the ADM-PCIE-8K5-FH: • From Flash

• ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AV14 FLASH_A24 1.8 AW14 FLASH_A25 1.8 AJ14 FLASH_A3 1.8 AL14 FLASH_A4 1.8 AL13 FLASH_A5 1.8 AL12 FLASH_A6 1.8 AM12 FLASH_A7 1.8 AM14 FLASH_A8 1.8 AN14 FLASH_A9 1.8 AL15 FLASH_ADV_L 1.8 AB9 FLASH_CE_L 1.8 AE11 FLASH_DQ0 1.8 AD10 FLASH_DQ1 1.8 AG12 FLASH_DQ10 1.8 AH12 FLASH_DQ11 1.8 AK13 FLASH_DQ1

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Signal Target FPGA Input I/O Standard pin FABRIC_CLK IO_L12P_T1U_GC_64 LVCMOS33 AM19 Table 6 : Fabric Clock 3.2.3 Programming Clock (EMCCLK) An 100MHz clock is fed into the EMCCLK pin to drive the BPI flash device during configuration of the FPGA. Signal Target FPGA Input I/O Standard pin REFCLK100M IO_L24P_T3U_N10_EMCCLK_65 LVCMOS18 AJ28 Table 7 : EMCCLK 3.2.4 SFP+ This board houses two 2x1 SFP+ cages, allowing for four total connections. Connectors SFP0 and SFP1 are located in MGT tile 227, while connectors SFP2 and SFP3 a

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual © 2018 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd. Head Office Address: 4 West Silvermills Lane, Edinburgh, EH3 5BD, UK Telephone: +44 131 558 2600 Fax: +44 131 558 2700 email: [email protected] website: http://www.alpha-data.com US Office 611 Corporate Circle Sui

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage AE30 DY 1.8 AH31 DZ 1.8 AD14 EMCCLK_B 1.8 AF30 EN_485/EN_232_L 1.8 D9 EXT_CLK_N MGT_CLK D10 EXT_CLK_P MGT_CLK AM19 FABRIC_CLK 3.3V use LVCMOS33 AK33 FB 1.8 AJ33 FEN 1.8 AL17 FIREFLY0_INT_L 3.3 AH17 FIREFLY0_MODPRS_L 3.3 AL18 FIREFLY0_RESET_L 3.3 H1 FIREFLY0_RX0_N MGT H2 FIREFLY0_RX0_P MGT G3 FIREFLY0_RX1_N MGT G4 FIREFLY0_RX1_P MGT F1 FIREFLY0_RX2_N MGT F2 FIREFLY0_RX2_P MGT E3 FIREFLY0_RX3_N MGT E4 FIREFLY0_RX3_P MGT AP19 FIREFLY0_SCL 3.3 AK18 FIREFLY0_SDA 3.3 AK17 FIREFLY0_SEL_L 3.3 H5 FIREFLY0_TX0_N MGT H6 FIREFLY0_TX0_P MGT G7 FIREFLY0_TX1_

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Pin Number Signal Name Bank Voltage D16 DDR4_0_ODT 1.2 H13 DDR4_0_PAR 1.2 A14 DDR4_0_RESET_N 1.2 K15 DDR4_0_TEN 1.2 AG22 DDR4_1_A0 1.2 AE20 DDR4_1_A1 1.2 AH23 DDR4_1_A10 1.2 AH22 DDR4_1_A11 1.2 AF23 DDR4_1_A12 1.2 AF22 DDR4_1_A13 1.2 AK23 DDR4_1_A14 1.2 AE21 DDR4_1_A15 1.2 AL22 DDR4_1_A16 1.2 AF20 DDR4_1_A17 1.2 AL20 DDR4_1_A2 1.2 AJ23 DDR4_1_A3 1.2 AK21 DDR4_1_A4 1.2 AM20 DDR4_1_A5 1.2 AN21 DDR4_1_A6 1.2 AD21 DDR4_1_A7 1.2 AG21 DDR4_1_A8 1.2 AP20 DDR4_1_A9 1.2 AR23 DDR4_1_ACT_N 1.2 AJ20 DDR4_1_ALERT_N 1.2 AK22 DDR4_1_BA0 1.2 AK20 DDR4_1_BA1 1.

• Alpha Data ADM-PCIE-8K5-FH, ADM-PCIE-8K5-FH User Manual Appendix A: Complete Pinout Table Pin Number Signal Name Bank Voltage U9 1V8_DIG INPUT AT18 AVR_B2U 3.3 AU16 AVR_HS_B2U 3.3 AU17 AVR_HS_CLK 3.3 AV19 AVR_HS_U2B 3.3 AW18 AVR_MON_CLK 3.3 AT17 AVR_U2B 3.3 AC11 CCLK 1.8 D14 DDR4_0_A0 1.2 F15 DDR4_0_A1 1.2 C14 DDR4_0_A10 1.2 E12 DDR4_0_A11 1.2 B14 DDR4_0_A12 1.2 J15 DDR4_0_A13 1.2 H12 DDR4_0_A14 1.2 B16 DDR4_0_A15 1.2 A15 DDR4_0_A16 1.2 L13 DDR4_0_A17 1.2 G12 DDR4_0_A2 1.2 E13 DDR4_0_A3 1.2 A13 DDR4_0_A4 1.2 C12 DDR4_0_A5 1.2 B12 DDR4_0_A6 1.2 F12 DDR4_0_A7 1.2 D13 DDR4_0_A8 1.2 C13 DDR4_0_A9 1.2 F13 DDR4_0_ACT_N 1.2 A12 DDR4_0_ALERT_N 1.2 B15 DDR4_0_BA0 1.2 F14 DDR4_0_

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