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ADLINK Technology PXI-2020 Operation & User’s Manual

ADLINK Technology PXI-2020 Manual Online:

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ADLINK Technology PXI-2020 User Manual
ADLINK Technology PXI-2020 User Guide
ADLINK Technology PXI-2020 Online Manual

Text of ADLINK Technology PXI-2020 User Guide:

  • ADLINK Technology PXI-2020, Copyright 2010 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, spe- cial, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copy- right. All rights are reserved

  • ADLINK Technology PXI-2020, ii Table of Contents Timebase Exporting ...................................................... 30 4.4 Trigger Sources ................................................................. 31 Software Trigger ........................................................... 31 External Digital Trigger ................................................. 31 PXI Star Trigger ............................................................ 32 PXI Trigger Bus ............................................................ 32 Trigger Signal Exporting ..................................

  • ADLINK Technology PXI-2020, Getting Started 11 2.3 Mechanical Drawing and I/O Connectors Figure 2-1: PXI-2020/2022 PCB Layout The ADLINK PXI-2020/2022 is packaged in a Euro-card form fac- tor compliant with PXI specifications measuring 160 mm in length and 100 mm in height (not including connectors). The connector types and functions are described as follows.

  • ADLINK Technology PXI-2020, Function Block and Operation Theory 29 an external timebase from the front panel connector AFI[0…7] or the SMB CLK IN. As you supply the timebase from external SMB CLK IN, which should be a sine wave or square wave signal. This signal is AC coupled with 50Ω input impedance and the valid input level is from 1 to 2 volts peak-to-peak. Note that the external clock should be continuous for fix sampling rate ADC operation. 4.3.3 External Clock from PXI Interfaces The PXI-2020/2022 can receive timebase via the PXI Trigger Bus line 0 by software setting

  • ADLINK Technology PXI-2020, 44 Function Block and Operation Theory 4.8.2 General Purpose Timer/Counter Modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the soft-ware-start is re-executed. The operat- ing theories under different modes are described as below. Mode 1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after the soft

  • 4Introduction Triggers Trigger Specifications Model Name PXI-2020/2022 Trigger Sources (refer to section 4.4 for details) (1)Software (2)AFI [0..7] (3)PXI Star Trigger (4)PXI Trigger Bus[5] (SSI) (5)SMB Trigger I/O (please refer to chapter 2.3 for details) *GA 3-8 can use (1), (2), (4), (5) as output signals. GA2 can use all options. Trigger Mode Pre-Trigger, Post-Trigger, Middle-T

  • ADLINK Technology PXI-2020, 40 Function Block and Operation Theory 4.7 Synchronizing Multiple Modules SSI (System Synchronization Interface) provides the DAQ timing synchronization between multiple cards. In PXI-2020/2022 series, we designed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI sig- nals are designed for card synchronization only, not for external devices. In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal c

  • Function Block and Operation Theory 39 4.6.4 Delay-trigger Acquisition Use delay-trigger acquisition to delay the data collection after the trigger event, as illustrated in Figure 4-14. The delay time is speci- fied by a 32-bit counter value so that the maximum delay time is the period of TIMEBASE X (232 - 1), while the minimum delay is the period of timebas

  • 36 Function Block and Operation Theory 4. ADCONV, the conversion signal to initiate a single con- version, which could be derived from internal counter, AFI[0] or SSI_ADCONV. Note that this signal is edge- sensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effec- tive conversion signal. Also note that the AFI[0] signal should

  • ADLINK Technology PXI-2020, 18 Signal Connections Legend: AIL1114 48AIH11 AGND 13 47 AGND AIL4 12 46 AIH4 AIL12 11 45 AIH12 AGND 10 44 AGND AIL5 9 43 AIH5 AIL13 8 42 AIH13 AGND 7 41 AGND AIL6 6 40 AIH6 AIL14 5 39 AIH14 AGND 4 38 AGND AIL7 3 37 AIH7 AIL15 2 36 AIH15 AGND 1 35 AGND Pin # Signal Name Reference Direction Description 58, 55, 52, 49, 46, 43, 40,37, 57, 54, 51, 48, 45, 42, 39, 36 AIH <0..15> AIL <0..15> Input Differential positive input for AI channel <0..15> 29, 31, 34, 68, DGND -------- -------- Digital ground 24, 21, 18, 15, 13, 9, 6, 3, 23, 20, 17, 14, 11, 8, 5, 2 AIL &l

  • 42 Function Block and Operation Theory The SSI/PXI mechanism 1. We adopt master-slave configuration for SSI/PXI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with the SSI function disabled. 2. For each timing signal, the SSI master doesn’t have to be in a single card. For example: We want to synchronize the A/D

  • ADLINK Technology PXI-2020, Introduction 3 1.2 Applications  Automotive Testing  Cable Testing  Transient signal measurement  ATE  Laboratory Automation  Biotech measurement 1.3 Specifications Basic Specifications Analog Input[1] Model Number PXI-2020 PXI-2022 Number of channels: (pro-grammable) 8 differential 16 differential A/D converter : AD7685 or equivalent Maximum sampling rate: 250 kS/s (each channel) Resolution: 16 bits Input coupling: DC Programmable input range: ±10V, ±2.5V Operational common mode voltage range: ±8V Overvoltage protection: Power on: Continuous ±30V Power off: Continuous ±30V FIFO

  • ADLINK Technology PXI-2020, 20 Signal Connections 3.2 Analog Input Signal Connection The PXI-2020/2022 provides 8/16 differential analog input chan- nels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and obtain more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals. 3.2.1 Types of Signal Sources Ground-Referenced Signal Sources A ground-referenced signal means it is connected in some way to the

  • ADLINK Technology PXI-2020, Introduction 5 Digital I/O General Purpose Timer/Counter (GPTC) Digital I/O Specifications Model Name PXI-2020/2022 Number of Channel 4 input/output Compatibility Input 3.3 V or 5 V TTL Output 3.3 V TTL Input Logic Levels Input low voltage: 0.8 V (max) Input high voltage: 2.0 V(min) Output Logic Levels Output low voltage: 0.4 V (max) Output high voltage: 2.8 V (min) Output Driving Capacity ±24 mA Power-on State Input, pull-low with 10KΩ resistor Data Transfer Polling mode Table 1-3: Digital I/O General Purpose Specifications Model Name PXI-2020/2022 Number of Cha

  • ADLINK Technology PXI-2020, Function Block and Operation Theory 41 The 3 internal timing signals could be routed to the PXI trigger bus through software drivers. Please refer to section 4.6.1 for detailed information of the 6 internal timing signals. Physically the signal routings are accomplished in the FPGA. Cards that are connected together through the PXI trigger bus, will still achieve synchroniza- tion on the 3 timing signals. Figure 4-15: SSI Mode Operation 4.7.1 SSI_TIMEBASE As an output, the SSI_TIMEBASE signal outputs the onboard LVTTL time-base through PXI trigger bus line 0. As an input, the PXI-2020/2022 accepts the

  • ADLINK Technology PXI-2020, 52 Important Safety Instructions  Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure there is adequate space around the system for ventilation when setting up the work area. Never insert objects of any kind into the ventila- tion openings.  To avoid electrical shock, always unplug all power and modem cables from the wall outlets before removing cov- ers.  Lithium Battery provided (real time clock battery) “CAUTION - Risk of explosion if battery is replaced by an incorrect type. Dispose used batteries as instructed in the instructions”  The equipment should be checked by service personnel if

  • ADLINK Technology PXI-2020, 24 Function Block and Operation Theory 4.2 Basic AI Acquisition In this section, the basic acquisition timing is explained. 4.2.1 Analog Input Path The following figure shows the block diagram of the single analog input path of a PXI-2020/2022. Each path provides a choice of 1G Ω input impedance or high impedance. The gain amplifier is opti- mized for ±10 V and ±2.5 V input range with low noise and high dynamic range. An anti-aliasing filter is also adopted to eliminate high frequency noise. The 16-bit ADC provides not only acc

  • 26 Function Block and Operation Theory Figure 4-3: Basic Acquisition Timing of PXI-2020/2022 4.2.3 AI Data Format When using an A/D converter, users should first know about the properties of the signal to be measured. Users can decide which channel to use and how to connect the signals to the card. Please refer to 4.2 for signal con-nections. The A/D acquisition is initiated by a trigger

  • ADLINK Technology PXI-2020, iv List of Figures List of Figures Figure 2-1: PXI-2020/2022 PCB Layout..................................... 11 Figure 3-1: Ground-referenced Source and Differential Input.... 21 Figure 3-2: Floating Source and Differential Input ..................... 22 Figure 4-1: PXI-2022 Functional Block Diagram........................ 23 Figure 4-2: PXI-2020/2022 Analog Input Path ........................... 24 Figure 4-3: Basic Acquisition Timing of PXI-2020/2022............. 26 Figure 4-4: PXI-2022 Timebase Source and Architecture. ........

  • ADLINK Technology PXI-2020, Calibration 49 5 Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The PXI-2020/2022 is factory calibrated before shipment by writ- ing the associated calibration constants of TrimDACs to the on- board EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capabil- ity. That means the calibration constants do not retain their values after the system power is turned off. Loading calibra

  • ADLINK Technology PXI-2020, 28 Function Block and Operation Theory 4.3 ADC Sampling Rate and TIMEBASE Control The PXI-2022 supports six timebase sources for analog input con- version: 1. On board Internal oscillator 2. External clock through front panel (AFI[0..7]) 3. External clock through front panel SMB CLK IN 4. PXI Star Trigger 5. PXI Trigger Bus Line 0 6. PXI 10M The following diagram shows the timebase architecture of the PXI- 2022. Figure 4-4: PXI-2022 Timebase Source and Architecture. 4.3.1 Internal Oscillator The PXI-2020/2022 equips a high stability, low jitter oscillator for the ADCs. The oscillators are 80 MHz for the PXI-2020/2022. 4.3.2 External Clock through Front Panel When

  • ADLINK Technology PXI-2020, 34 Function Block and Operation Theory 4.5 User-controllable Timing Signals In order to meet the requirements for user-specific timing and the re-quirements for synchronizing multiple cards, the PXI-2020/2022 series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The entire DAQ timing of the PXI-2020/2022 series is composed of a bunch of counters and trigger signals in the FPGA. These tim- ing signals are related to the A/D conversions and Timer/Counter applications. These timing signals can be inputs to or outputs from the

  • ADLINK Technology PXI-2020, Function Block and Operation Theory 33 4.4.5 Trigger Signal Exporting The PXI-2020/2022 can export trigger signals to following connec- tors/bus: SMB TRG IO on front panel, AFI0 on front panel and PXI Trigger Bus Line 5. The TRG IO on the front panel can also be programmed to output the trigger signal when the trigger source is from software trigger, Auxiliary Function Interface, PXI Star Trig- ger, or PXI Trigger Bus Line 5. The timing characteristic is in Fig- ure 4-8. Figure 4-8: TRG IO Output Signal Timing TRG IO (Output) Tw Tw = 3 TIMEBASE Clocks

  • ADLINK Technology PXI-2020, 12 Getting Started SMB Connector  SMB Connector 1: TRG IO  SMB Connector 2: Sync CLK_OUT1  SMB Connector 3: Sync CLK_OUT0  SMB Connector 4: CLK IN Connector Direction Type Description/Function TRG IO Input Output SMB The TRG IO is a bidirectional port for external digi- tal trigger input or output. CLK OUT1 Output SMB The CLK OUTOUT 1 is a 50Ω, DC-coupled output; CLK_OUT0 and CLK_OUT1 is from the same source. CLK OUT0 Output SMB The CLK OUTPUT 0 is a 50Ω, DC-coupled output; CLK_OUT0 and CLK_OUT1 is from the same source. CLK IN Input SMB The CLK IN is a 50Ω, AC-coupled external time- base in

  • ADLINK Technology PXI-2020, ADLINK Technology (Europe) GmbH Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: [email protected] ADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: [email protected] ADLINK Technology Japan Corporation Address: 151-0072 ᧲੩ㇺᷦ⼱඙ᐈ䊱⼱㩷 1-1-2 ᦺᣣ↢๮ᐈ䊱⼱䊎䊦 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan Tel: +81-3-4455-3722

  • Function Block and Operation Theory 37 4.6 Trigger Modes There are four trigger modes working with trigger sources to initi- ate different data acquisition timing when a trigger event occurs. They are described in this section. 4.6.1 Post-trigger Acquisition Use post-trigger acquisition when you want to collect data after the trigger event, as illustrated in Figure 4-10

  • ADLINK Technology PXI-2020, 48 Function Block and Operation Theory Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-23 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. Figure 4-23: Mode 8 Operation 4 4 3 3 2 1 0 2 1 S o f t w a r e s t a r t 0 3 2 1 0 2 1 1 0 3 G a t e C L K C o u n t v a l u e O U T

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