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Samsung KS8910 Operation & User’s Manual

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Samsung KS8910 User Manual
Samsung KS8910 User Guide
Samsung KS8910 Online Manual

Text of Samsung KS8910 User Guide:

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER PRODUCT OVERVIEW 1-1 Preliminary Spec. ver 1.4 1 PRODUCT OVERVIEW INTRODUCTION The KS8910 10Base-T/100Base-TX Ethernet transceiver is fully compliant with the IEEE 802.3u specification, provides configurable 100Mbs support for Category 5 unshielded twisted pair (UTP) and supports 10Mbs operation on Category 3 UTP or Category 5 UTP. The transceiver provides an electrical interface between the Media Independent Interface (MII) of the Media Access Controller (MAC) and the physical wire pair, and includes support for the basic and extended register set of station mana

  • Samsung KS8910, A-5 KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX Preliminary Spec. ver 1.4 • OC12 - 622.08 Mbit/s Optical Carrier 12, SONET Synchronous Transport Signal STS-12. Twelve byte- interleaved STS-1 signals. • OC48 - 2488.32 Mbit/s Optical Carrier 48, SONET Synchronous Transport Signal STS-48. 48 byte-interleaved STS-1 signals. • Octet - byte. • OSI - Open System Interconnection reference model layers adopted by the ISO application, presentation, session, transport, network, data link (composed of LLC and MAC layers of LAN CSMA/CD), and physical (composed of PLS and PMA layers of LAN CSMA/CD, connected by AUI). Also, Obsolete Systems Interconnect. 1 • Packet - According

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS 2-7 Preliminary Spec. ver 1.4 NOTES: 1.t/s: (sustained)tri-state, 5T: 5V Tolerance, 2.PD: Pull Down, PU: Pull Up 3.P: Power Supply 4.G: Ground Signal Pin Number I/O Description Power and Ground Signals VDDDIG 2,47 P 3.3V Power Supply for Digital Internal Block VDDIO 10,39,57 P 3.3V Power Supply for Digital I/O Block VDDTXA 14 P 3.3V Power Supply for Analog Block VDDRXA 37 P 3.3V Power Supply for Analog Block VDDREF 28 P 3.3V Power Supply for Analog Reference Block VDDTXQ 16 P 3.3V Power Supply for

  • Samsung KS8910, A-7 KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX Preliminary Spec. ver 1.4 • TCP - Transmission Control Protocol, a connection-oriented, reliable, full-duplex, virtual circuit byte-stream facility for a user process. Uses IP. Part of the TCP/IP protocol suite. • TCP/IP - Transmission Control Protocol/Internet Protocol, the DARPA Internet protocol suite. • Type 1 cable - Shielded, two-pair cable. • Type 3 cable - Unshielded, twisted-pair cable. • UDP - User Datagram Protocol, a connectionless, unreliable datagram facility for a user process. Use

  • Samsung KS8910, 100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 4-2 Preliminary Spec. ver 1.4 PHYSICAL MEDIUM ATTACHMENT SUBLAYER (PMA) The PMA provides a medium-independent means for the PCS and other bit-oriented clients to support the use of a range of physical media. The KS8910’s PMA performs the following functions: • Mapping of transmit and receive code-bits between the PMA’s client and the underlying PMD • Generating a control signal indicating the availability of the PMD to a PCS or other client and synchronizing with Auto-Negotiation • Scrambling and descrambling of the transmit code-bits and the receive code-bits, respective

  • Samsung KS8910, A-4 APPENDIX KS8910 100/10 Mbps ETHERNET TRANSCEIVER Preliminary Spec. ver 1.4 • LAN - Local Area Network. • Little endian - The byte at memory address 0 contains the least-significant bits. Used by Intel x86, DEC Vax, and DEC PDP-11. • LLC - Logical Link Control layer of LAN CSMA/CD. The upper half of the OSI (which see) reference model data link layer, between the MAC and the network layer. • Locally administered address - An Ethernet address whose second bit transmitted, used to distinguish between locally or globally administered addresses, is set to 1, indicating a locally administered address. If an address is

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS 8-3 Preliminary Spec. ver 1.4 D.C ELECTRICAL CHARACTERISTICS MII PADS SPECIFICATION V DD =3.3V¡¾10%, T A =0 to 125°C(5.0V Tolerant I/O) NOTES : 1. Only leakage Current 100BASE-TX TRANSCEIVER SPECIFICATION V DD =3.3V¡¾10%, T A =0 to 125°C(5.0V Tolerant I/O) NOTES : 1. Typical Value are at 25 °C and are for design aid only;not guaranteed and not suject to prodiction testing. 2. Measured at the line side of the transformer, line replaced by 10

  • Samsung KS8910, PRELIMINARY SPECIFICATION KS8910 100/10 Mbps ETHERNET CONTROLLER xi List of Tables Table Number Title Page Number 2-1 KS8910 Signal Descriptions .............................................................................................. 2-4 4-1 4B/5B Coding of KS8910 .................................................................................................. 4-5 4-2 5B/4B Outputs.................................................................................................................... 4-6 6-1 Transmit Clocks Generated by the Frequency Synthesizer .............................................. 6-4 7-1 Address Mapping .....................

  • 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 6-6 Preliminary Spec. ver 1.4 ADAPTIVE EQUALIZER High frequency attenuation and group delay variation introduced by the twisted pair degrades the data signal. The adaptive equalizer restores these high frequency components and restores the data to a condition suitable for clock recovery and data slicing. The signal arriv

  • KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX DIGITAL BLOCKS 4-5 Preliminary Spec. ver 1.4 Table 4-1. 4B/5B Coding of KS8910 Code Type 4B Code [3:0] Name 5B Symbol [4:0] Interpretation DATA 0000 0 11110 “0” Data 0001 1 01001 “1” Data 0010 2 10100 “2” Data 0011 3 10101 “3” Data 0100 4 01010 “4” Data 0101 5 01011 “5” Data 0110 6 01110

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS 7-13 Preliminary Spec. ver 1.4 MAP TABLE REGISTER 0 : REGISTER 19 [MPTBLE0] 13h MAP TABLE REGISTER 1 : REGISTER 20 [MPTBLE1] 14h 13h 15 0 Map_Table • Map_Table Map Table PRF Mux output value of PH~PA is desided by Map_Table[26:0]value. The initial value of the Map_Table[15:0] is 0000 0000 0000 0000. Map_Table[26:0]=MPTBLE0[15:0],MPTBLE1[10:0]. 14h 15 14 13 12 11 10 0 Iadj_UP Iadj_S1 IadjS0 SS_Mux Sel_BG Map_Table • Iadj_UP PrefilterCnt Data Input Signal comparing level control(RX path data jitter control) The initial value of tIadj_S1[15:13] is

  • Samsung KS8910, 100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 4-14 Preliminary Spec. ver 1.4 PHYSICAL MEDIUM DEPENDENT SUBLAYER The majority of the PMD is either analog or mixed-signal and is, therefore, not described in this charter, though a resume is given just below. A detailed description of this part of the circuitry can be found in chapter 6 of this document. In the transmit direction the serial data stream is converted from NRZI to MLT-3. In the inbound direction the DC level of the signal is first restored, then it runs through an equalizer and

  • Samsung KS8910, 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 6-8 Preliminary Spec. ver 1.4 line termination is performed by the circuit shown in Figure6-5. RECEIVE CLOCK RECOVERY(20MHZ,DPLL) An on-chip frequency synthesis PLL recovers a 20MHz clock using the frequency reference from receiving data. The PLL uses digital techniques to create the optimum clock for re-timinig the received data.

  • REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 7-16 Preliminary Spec. ver 1.4 100BASE-T STATUS REGISTER : REGISTER 25 [TXSR] 19h 19h 15 14 13 12 11 10 9 8 0 XMT RCV COL Resreved LNKST FD Reserved • FD Full Duplex 1 = Full Duplex. 0 = Half Duplex. • LNKST Link status 1 = 100Base-TX link is up. 0 = 100Base-TX link is down. • COL Colision Detected 1 = Collision detected.

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS 8-11 Preliminary Spec. ver 1.4 MII-MANAGEMENT INTERFACE TIMING Figure 8-8. MII-Management Interface Timing Diagram Table 8-13. MII-Management Interface Timing Symbol Conditions Min Typ Max Unit t1 MDC Minimum High Time 160 - - ns t2 MDC Minimum Low Time 160 - - ns t3 MDC Period 400 - - ns t4 MDC rise to MDIO valid 0 - 300 ns t5 MDIO Setup to MDC 10 - - ns t6 MDIO Hold after MDC 10 - - ns t 1 t 2 MDC MDIO (output) t 3 t 4 MDC MDIO (Input) t 5 t 6

  • Samsung KS8910, 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 6-2 Preliminary Spec. ver 1.4 The 10Base-T Analog block interfaces the digital logic to the transmit and receive twisted-pair interfaces. A block diagram of the 10Mbit/s data path is shown in Figure6-2. The 10Mbit/s digital components are described in Chapter 5. The analog components are shaded and are described in this chapter. The main transmit analog blocks are the clock generator, the wave shaper, and the driver. The receive blocks include a receive buffer . In addition, the receive circuit detects the presence of on the receive twisted pair and supplies status signals to the auto-negotiation circuit indicating lock

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX DIGITAL BLOCKS 4-11 Preliminary Spec. ver 1.4 Descrambler The Descrambler shall decode the NRZ cipher-text bit stream from the MLT-3 decoder. The cipher-text bit stream shall be decoded by addition (modulo 2) of a key stream to produce a plain-text bit stream. The key stream shall be the periodic sequence of 2047 bits generated by the recursive linear function X[n] = X[n-11] + X[n-9] (modulo 2). The descrambler shall generate the specified key stream while it is synchronized. The descrambler is defined to be synchronized while the descrambler key stream added to a sequence of ci

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS 2-3 Preliminary Spec. ver 1.4 PIN ASSIGNMENTS Figure 2-2. KS8910 Pin Assignments 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSSDIG VDDDIG LEDC[ID4] LEDL[ID3] LEDT[ID2] LEDR[ID1] LEDS[ID0] FDPLX VSSIO VDDIO XTAL_OUT XTAL_IN VSSTXA VDDTXA VSSTXQ VDDTXQ TPIP TPIN SUBANA SP_SEL VDDREF VSSREF RB RBGND AN_EN TPON VSSDRV TPOP SUBDRV TPOB VDDDRV VSSDRV Rx_DV Rx_clk Rx_er Tx_er Tx_clk SUBDIG SUBIO VSSIO VDDIO Tx_en TxD0 TxD1 T

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS 8-15 Preliminary Spec. ver 1.4 10BASE-T NORMAL LINK PULSE TIMING Figure 8-12. 10Base-T Normal Link Pulse Timing Diagram Table 8-17. 10Base-T Normal Link Pulse Timing Symbol Conditions Min Typ Max Unit t1 Normal Link Pulse Width (10Base-T) - 100 - ns t2 COL Heartbeat assertion duration 8 10 24 ms TPOP t 1 t 2

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T DIGITAL BLOCKS 5-5 Preliminary Spec. ver 1.4 LOOP-BACK FUNCTION The 10BASE-T Transceiver provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the 10BASE-T Transceiver from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. The normal loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber

  • Samsung KS8910, REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 7-14 Preliminary Spec. ver 1.4 ANALOG CONTROL REGISTER 0 : REGISTER 21 [ANARC0] 15h ANALOG CONTROL REGISTER 1 : REGISTER 22 [ANARC1] 16h 15h 15 8 7 0 QinH ~ QinA PinH ~ PinA • QinA Equalizer HPF s/w The fixed output value of prefilter counter when Use_PQ(Reg(16.1)=1 • PinA Equalizer BPF s/w Thefixed output value of prefilter counter. 16h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPDNB S1 S0 QFCBP FR PDWS PDSQ PDSG PDR PDPF PRRE PDRP PDTP PDDRV USEPQ Qinl • Qinl TheMSB value of

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER FINCTIONAL BLOCKS 3-5 Preliminary Spec. ver 1.4 10BASE-T DIGITAL BLOCK The 10BASE-T digital block interfaces a back-end controller to a twisted-pair (TP) cable. The controller interface includes transmit and receive clock and Manchester data as well as mode control logic and signaling. And the 10BASE-T Transceiver has synthesized clocks derived from a 25 MHz crystal oscillator and five LED drivers for visual status reporting. The 10BASE-T Transmit function refers to data transmitted to the twisted-pair network.The Receive function refers to data received by the back end from

  • Samsung KS8910, PRELIMINARY SPECIFICATION x KS8910 100/10 Mbps ETHERNET CONTROLLER List of Figures Figure Number Title Page Number 1-1 KS8910 PHY Transceiver (64-QFP-1414 Package) .........................................................1-1 1-2 Ethernet System Overview Diagram with Emphasis on MDI .............................................1-3 1-3 100/10 Mbps Ethernet Transceiver Block Diagram ...........................................................1-3 2-1 External Signals ................................................................................

  • Samsung KS8910, KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX ANALOG BLOCKS 6-7 Preliminary Spec. ver 1.4 A differential loop filter is integrated on chip. This loop filter forms a second-order loop. Higher order high frequency poles are added by on-chip filters. The VCO gain is 140MHz/Volt, and the charge pump current is 20uA. The recommended components result in a loop bandwidth of 250KHz and a phase margin of 75 degrees. SIGNAL DECTECTOR The Signal Detector monitors signal amplitude on cable and inform Digital Block about existence of 100 Rx_code_bit by checking link_status. Threshold of Detect Assertio

  • Samsung KS8910, ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 8-8 Preliminary Spec. ver 1.4 MII/10BASE-T RECEIVE TIMING Figure 8-5. MII/10Base-T Receive Timing Diagram Table 8-10. MII/10Base-T Receive Timing Symbol Conditions Min Typ Max Unit t1 TPI in to RxD out (Rx latency) - 4 - us t2 RxD,Rx_DV,Rx_er Setup to Rx-clk rise 10 - - ns t3 RxD,Rx_DV,Rx_er Hold form Rx-clk rise 10 - - ns t4 CrS asserted to RxD,Rx_DV,Rx_er asserted - 0 - us t5 RxD,Rx_DV,Rx_er de-asserted to CRS de-asserted - 0 - us t6 TPIP in to CRS asserted 0 4 - us t7 TPIP quie

  • REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 7-2 Preliminary Spec. ver 1.4 REGISTER DEFINITIONS NOTE: * The addresses given in table 8-1 are in decimal(hex) while they are hexadecimal in the following tables. * B/E : Basic/Extended Table 8-1. Address Mapping Register Name Address(Hex) Initial Value B/E BMCR Base Mode Control Register 0(00h) 0011_0100_0000_0000 B BMSR Base

  • KS8910 100/10 Mbps ETHERNET TRANSCEIVER PRODUCT OVERVIEW 1-3 Preliminary Spec. ver 1.4 ETHERNET 10BASE-T AND 100BASE-TX BLOCK DIAGRAM Figure 1-2. Ethernet System Overview Diagram with Emphasis on MDI Figure 1-3. 100/10 Mbps Ethernet Transceiver Block Diagram Processor Transformer MII 10Base-T 100Base-TX P C I B U S 10/100Mbps PHY 10/100Mbps MAC KS8920 KS8910 Auto-Negotiatio

  • Samsung KS8910, REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 7-8 Preliminary Spec. ver 1.4 AUTO-NEGOTIATION LINK PARTNER ABILITY : REGISTER 5 [ANLPAR] 05h : Base Page [ANLPAR] 05h : Next Page 05h 15 14 13 12 11 10 9 8 7 6 5 4 0 NP ACK RF Reserved T4 100_FD 100_HD 10_FD 10_HD Selector • Selector Protocol Selector =00001: These bits contain the binary encoded protocol selector supported by the Link Partner. • 10_HD 10Base-T Half Duplex If set(=1), Linlk Parter supports 10Base-T Half Duplex mode. • 10_FD 10Base-T Half Duplex If set(=1), Link Parter supports 10

  • KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS 2-1 Preliminary Spec. ver 1.4 2 EXTERNAL SIGNALS OVERVIEW Figure2-1 shows the 44 external signals for the 10/100 Mbit/s Ethernet Physical Layer Transceiver, divided into functional groups. Power and ground pins need to be added to this signal list. The device will require a 64 pin package. This chapter groups the signal definitions by fu

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