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Panasonic MICROCOMPUTER MN103S Operation & User’s Manual

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Panasonic MICROCOMPUTER MN103S Manual Online:

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Panasonic MICROCOMPUTER MN103S User Manual
Panasonic MICROCOMPUTER MN103S User Guide
Panasonic MICROCOMPUTER MN103S Online Manual

Text of Panasonic MICROCOMPUTER MN103S User Guide:

  • Chapter 7 I/O Port VII - 32 Ports 7.3 Ports 7.3.1 Description (Port 1) ■ General Port Setup Each bit can be set individually as either an input or output by the port 1 I/O control register (P1DIR). The control flag of the P1DIR register is set to “1” for output mode and to “0” for input mode. To read input data of a pin, set the control flag of the P1DIR to “0” and read the va

  • Panasonic MICROCOMPUTER MN103S, Chapter 13 Serial Interface 2 XIII - 4 Control Registers 13.2 Control Registers 13.2.1 Registers Table: 13.2.1 shows registers that control serial interface 2. Table:13.2.1 Serial Interface 2 Control Registers .. When changing the setting value of the mode register, rewrite it after setting the serial forced reset. (Both the SC2BIS flag and the SC2BOS flag of the SC2CTR1 registers are set to "0".) .. Register Address R/W Access size Function Page Serial 2 SC2RB 0x0000A12C R 8,16 Serial interface 2 reception

  • Panasonic MICROCOMPUTER MN103S, Chapter 9 16-bit Timer Control registers IX - 11 ■ Timer 13 Prescaler Control Register (TM13PSC: 0x0000A2B4) [8, 16-bit Access Register] ■ External Prescaler Control Register 1 (TMEXPSC16: 0x0000A218) [8, 16-bit Access Register] bp 7 6543210 Flag TM PSCNE ------- At reset 0 0000000 Access R/WRRRRRRR bp Flag Description Setting condition 7 TMPSCNE Prescaler operation enable 0: Operation disabled 1: Operation enabled 6-0 - - - bp 7 6543210 Flag TM PSCNE ------- At reset 0 0000000 Access R/WRRRRRRR bp Flag Description Setting condition 7 TMPSCNE Prescaler operation enable 0: Operation disabled 1: Operation enabled 6-0 - - -

  • Panasonic MICROCOMPUTER MN103S, Chapter 8 8-bit Timer Control Registers VIII - 23 ■ Timer 5 Mode Register (TM5MD: 0x0000A1A1) [8-bit Access Register] bp 76543210 Flag TM5 CNE TM5 LDE ---TM5 CK2 TM5 CK1 TM5 CK0 At reset 00000000 Access R/W R/W R R R R/W R/W R/W bp Flag Description Set condition 7 TM5CNE Timer operation enable 0: Operation disabled 1: Operation enabled 6TM5LDE Timer initialization 0: Normal operation 1: Initialization TM5BR value is loaded into TM5BC. Timer output 5 is set to “L” level. 5-3 - - - 2-0 TM5CK2 TM5CK1 TM5CK0 Count clock source select

  • Panasonic MICROCOMPUTER MN103S, Chapter 9 16-bit Timer Control registers IX - 19 9.2.4 Timer Mode Registers These are readable/writable registers which control the timer 8 to timer 13. The timer compare/capture A mode register controls the compare/capture A register, and the timer compare/capture B mode register controls the com- pare/capture B register.

  • Panasonic MICROCOMPUTER MN103S, Chapter 8 8-bit Timer Control Registers VIII - 9 Timer 4 TM4BR 0x0000A1A8 R/W 8 TImer 4 base register VIII-14 TM4BC 0x0000A1B0 R 8 Timer 4 binary counter VIII-16 TM4MD 0x0000A1A0 R/W 8 Timer 4 mode register VIII-22 G5ICR 0x00008914 R/W 8,16 Group 5 interrupt control register V-16 P3MD 0x0000A033 R/W 8 Port 3 output mode register VII-16 P3DIR 0x0000A023 R/W 8 Port 3 I/O control register VII-15 Timer 5 TM5BR 0x0000A1A9 R/W 8 Timer 5 base register VIII-14 TM5BC 0x0000A1B1 R 8 Timer 5 binary counter VIII-

  • Panasonic MICROCOMPUTER MN103S, SALES OFFICES NORTH AMERICA  U.S.A. Sales Office: Panasonic Industrial Company [PIC]  San Diego Office: 9444 Balboa Avenue, Suite 185, San Diego, California 92123, U.S.A. Tel:1-858-503-2965 Fax:1-858-715-5545  New Jersey Office: 3 Panasonic Way Secaucus, New Jersey 07094, U.S.A.  Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847, U.S.A.  San Jose Office: 2033 Gateway Place, Suite 200, San Jose, California 95110, U.S.A  Canada Sales Office: Panasonic Canada Inc. [PCI] 5770 Ambler Drive 27 Mississauga, Ontario L4W 2T3

  • Panasonic MICROCOMPUTER MN103S, Chapter 14 A/D Converter XIV - 22 Control Registers ■ A/D1 Conversion Data Buffer 8 (AN1BUF08: 0x0000A468) [16-bit Access Register] ■ A/D1 Conversion Data Buffer 9 (AN1BUF09: 0x0000A46C) [16-bit Access Register] ■ A/D1 Conversion Data Buffer 0B (AN1BUF0B: 0x0000A470) [16-bit Access Register] bp 1514131211109876543210 Flag ------ AN1 BUF 89 AN1 BUF 88 AN1 BUF 87 AN1 BUF 86 AN1 BUF 85 AN1 BUF 84 AN1 BUF 83 AN1 BUF 82 AN1 BUF 81 AN1 BUF 80 At reset 000000×××××××××× Access RRRRRRRRRRRRRRRR bp Flag Description Setting condition 15-10 - - - 9-0 AN1BUF89 to AN1BUF80 A/D1 conversion result of ADIN08 pin A/D1 conversion result of ADIN08 pin

  • Panasonic MICROCOMPUTER MN103S, Chapter 13 Serial Interface 2 Operation XIII - 23 13.3.3 Setup Example ■ Transmission/Reception Setup Example Here is the setup example for transmission/reception of clock synchronous communication with serial interface 2. Table: 13.3.7 shows the conditions for transmission/reception. Table:13.3.7 Conditions of Synchronous Serial Interface Transmission/Reception Setting item Description SBI2/SBO2 pin setting Independent (3 channels) Transfer bit count 8 bits Start condition Without start condition First transfer bit MSB Input edge Rising Output edge Falling Clock Clock master Clock source IOCLK/2 1/16 di

  • Panasonic MICROCOMPUTER MN103S, Chapter 16 Appendix Instruction Set XVI - 25 UDF20 imm16,Dn UDF21 imm16,Dn UDF22 imm16,Dn UDF23 imm16,Dn UDF24 imm16,Dn UDF25 imm16,Dn UDF26 imm16,Dn UDF27 imm16,Dn UDF28 imm16,Dn UDF29 imm16,Dn UDF30 imm16,Dn UDF31 imm16,Dn UDF32 imm16,Dn UDF33 imm16,Dn UDF34 imm16,Dn UDF35 imm16,Dn UDF00 imm32,Dn UDF01 imm32,Dn UDF02 imm32,Dn UDF03 imm32,Dn UDF04 imm32,Dn UDF05 imm32,Dn UDF06 imm32,Dn UDF07 imm32,Dn UDF08 imm32,Dn UDF09 imm32,Dn UDF10 imm32,Dn UDF11 imm32,Dn UDF12 imm32,Dn UDF13 imm32,Dn UDF14 imm32,Dn UDF15 imm32,Dn UDF20 imm32,Dn UDF21 imm32,Dn UDF22 imm32,Dn UDF23 imm32,Dn UDF24 imm32,Dn UDF25 imm32,Dn UDF26 imm32,Dn UDF27 imm32,Dn imm16

  • Panasonic MICROCOMPUTER MN103S, Chapter 16 Appendix XVI - 84 Special Function Registers List 0x7FF00118 RCR1DR RC1 DT63 RC1 DT62 RC1 DT61 RC1 DT60 RC1 DT59 RC1 DT58 RC1 DT57 RC1 DT56 RC1 DT55 RC1 DT54 RC1 DT53 RC1 DT52 RC1 DT51 RC1 DT50 RC1 DT49 RC1 DT48 VI-8 RC1 DT47 RC1 DT46 RC1 DT45 RC1 DT44 RC1 DT43 RC1 DT42 RC1 DT41 RC1 DT40 RC1 DT39 RC1 DT38 RC1 DT37 RC1 DT36 RC1 DT35 RC1 DT34 RC1 DT33 RC1 DT32 RC1 DT31 RC1 DT30 RC1 DT29 RC1 DT28 RC1 DT27 RC1 DT26 RC1 DT25 RC1 DT24 RC1 DT23 RC1 DT22 RC1 DT21 RC1 DT20 RC1 DT19 RC1 DT18 RC1 DT17 RC1 DT16 RC1 DT15 RC1 DT14 RC1 DT13 RC1 DT12 RC1 DT11 RC1 DT10 RC1 DT9 RC1 DT8 RC1 DT7 RC1 DT6 RC1 DT5 RC1 DT4 RC1 DT3 RC

  • Panasonic MICROCOMPUTER MN103S, Chapter 16 Appendix XVI - 22 Instruction Set RETF RETS JSR (An) JSR label RTS RTI TRAP NOP SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ D0,mem32(SP-16)→ D1, mem32(SP-20)→ A0,mem32(SP-24)→ A1, mem32(SP-28)→ MDR,mem32(SP-32)→ LIR, mem32(SP-36)→ LAR SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ reg3,mem32(SP-16)→ D0, mem32(SP-20)→ D1,mem32(SP-24)→ A0, mem32(SP-28)→ A1,mem32(SP-32)→ MDR, mem32(SP-36)→ LIR,mem32(SP-40)→ LAR, SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ D2,mem32(SP-8)→ D

  • Chapter 16 Appendix Instruction Set XVI - 21 RET RETF SP + imm8(zero_ext) → SP, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ D0,mem32(SP-16)→ D1, mem32(SP-20)→ A0,mem32(SP-24)→ A1, mem32(SP-28)→ MDR,mem32(SP-32)→ LIR, mem32(SP-36)→ LAR,mem32(SP) → PC SP + imm8(zero_ext) → SP, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ reg3,mem32(SP-16)→ D

  • Chapter 7 I/O Port Control Registers VII - 27 ■ Port 8 Pull-up Resistor Control Register (P8PLU: 0x0000A048) [8-bit access register] bp 76543210 Flag Rese rved Rese rved Rese rved Rese rved P83R P82R P81R P80R At reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W bp Flag Description Set condition 7-4 Reserved - Write "0" 3-0 P83R to P80R Pull-up resistor selection 0: Not ad

  • Panasonic MICROCOMPUTER MN103S, Chapter 8 8-bit Timer Overview VIII - 3 Timer 14 Timer 15 Timer 16 Timer 17 Page Interrupt cause NTMIRQ14 NTMIRQ15 NTMIRQ16 NTMIRQ17 - Interval timer VIII-32 Timer output - - - VIII-36 Event count - - - VIII-38 Baud rate timer - VIII-32 Cascade connection - Connect with timer 14 Connect with timer 15 Connect with timer 16 VIII-40 Counter source IOCLK IOCLK/8 IOCLK/32 IOCLK/128 Timer 15 underflow Timer 16 underflow IOCLK IOCLK/8 IOCLK/32 Timer 14 underflow Timer 16 underflow Cascading with timer 14 IOCLK IOCLK/8 IOCLK/32 IOCLK/128 Timer 14 underflow Timer 15 un

  • Panasonic MICROCOMPUTER MN103S, Chapter 1 Overview Electrical Characteristics I - 23 1.5.5 AC Characteristics Figure:1.5.3 Power-On Sequence .. * Insert capacitor of over 0.1 µF between NRST pin and ground. .. Power-On sequence Parameter Symbol Conditions Limits Unit Min. Typ. Max. E1 Reset signal pulse width (NRST) tRSTW - 1 - - ms E2 Reset release timing (NRST) tRSTS - 1 - - ms V DD NRST NRST tRSTW tRSTS

  • Panasonic MICROCOMPUTER MN103S, Chapter 1 Overview I - 8 Hardware Functions - Transfer clock source 1/2, 1/4, 1/16, and 1/64 of timer 14 underflow, 1/2, 1/4, 1/16, and 1/64 of timer 15 underflow, 1/2, 1/4, 1/16, and 1/64 of timer 16 underflow, IOCLK/2, IOCLK/4, SBT2 pin - Can be selected as the first bit to be transferred, Any transfer size from 1 to 8 bits can be selected. - Continuous transmission, reception, and transmission/reception - Maximum transfer rate: 5.0 Mbps Full duplex UART - Parity error, overrun error and flaming error detection - Transfer clock source 1/32, 1/64, 1/256, and 1/1024 of timer 14 un

  • Panasonic MICROCOMPUTER MN103S, Chapter 9 16-bit Timer IX - 56 Timer Output TM8BC counter counts up. When the TM8BC counter and the TM8CA register match, the condition of the output pin (TM8AIO) is inverted at the rising edge of the next count clock. The value of the TM8BC counter is initialized to 0x0000 and starts to count up again. Timer output cycle = (TMnCA value + 1) × Count clock source cycle × 2 (9) Initialize the timer 8 TM8MD(0x0000A200) bp6: TMLDE=1 (9) Set the TMLDE flag of the TM8MD register to “1” to initialize the timer 8. The value of the compare register buffe

  • Panasonic MICROCOMPUTER MN103S, Chapter 13 Serial Interface 2 Operation XIII - 11 13.3 Operation 13.3.1 Serial Interface 2 Operation Serial interface 2 is used as clock synchronous and full duplex UART serial interface. 13.3.2 Clock Synchronous Serial Interface ■ Activation Factors for Communication Table: 13.3.1 shows activation factors for communication. In the case of master communication, a transfer clock is generated by setting data to the transfer data buffer SC2TB or by receiving a start condition. Signal input from the SBT2 pin is masked inside serial interface to prevent operating errors by noise, except d

  • Chapter 2 CPU Basics Memory Space II - 19 2.6.3 Register Map Table:2.6.2 shows the register map. Table:2.6.2 Branch Instructions FEDCBA9876543210 x'0000800X Interrupt vector x'0000801X x'0000804X x'0000807X x'0000820X RSTCTR WDCTR WDBC Watchdog x'0000828X CKCTR Clock generator x'0000890X Interrupt control x'0000891X x'0000892X x'0

  • Panasonic MICROCOMPUTER MN103S, Chapter 9 16-bit Timer Control registers IX - 13 9.2.3 Programmable Timer Registers Timer 8 to timer 11 each have 16-bit programmable timer registers. Programmable timer registers are composed of the binary counter (TMnBC), the compare/capture A register (TMnCA) and the compare/capture B register (TMnCB). ■ Timer 8 Binary Counter (TM8BC: 0x0000A210) [16-bit Access Register] This is a binary counter of timers and a 16-bit readable only register. Table:9.2.2 shows updated timing (0x0000 clear, etc.) of the binary counter.

  • Panasonic MICROCOMPUTER MN103S, Chapter 1 Overview I - 24 Electrical Characteristics Figure:1.5.4 Interrupt signal timing Interrupt signal input timing V DD =5.0 V V SS = 0.0 V Ta= -40 °C to +85 °C CL= 50 pF Tmclk = 1/MCLK Tsmp = n/IOCLK n = 4,8 ,16,32 Parameter Symbol Conditions Limits Unit Min. Typ. Max. E3 Interrupt signal pulse width(IRQn) In not using noise filter tlRQW1 - Tmclk x 3 *1 *1.When no noise filter is used, the minimum pulse width is determined by system clock(MCLK). Maintain the interrupt signal for a minimum of 3 cycles of MCLK. --ns E4 Interrupt signal pulse wi

  • Panasonic MICROCOMPUTER MN103S, Chapter 14 A/D Converter Control Registers XIV - 17 14.2.5 Data Buffers A/D conversion result (10 bits) is stored in A/D conversion data buffers. ■ A/D0 Conversion Data Buffer 0 (AN0BUF00: 0x0000A410) [16-bit Access Register] ■ A/D0 Conversion Data Buffer 1 (AN0BUF01: 0x0000A414) [16-bit Access Register] ■ A/D0 Conversion Data Buffer 2 (AN0BUF02: 0x0000A418) [16-bit Access Register] bp 1514131211109876543210 Flag ------ AN0 BUF 09 AN0 BUF 08 AN0 BUF 07 AN0 BUF 06 AN0 BUF 05 AN0 BUF 04 AN0 BUF 03 AN0 BUF 02 AN0 BUF 01 AN0 BUF 00 At reset 000000×××××�

  • Panasonic MICROCOMPUTER MN103S, Chapter 14 A/D Converter XIV - 2 Overview 14.1 Overview This LSI has an A/D converter with 10 bit resolutions and up to 16-channel analog signals can be processed with 3 converters. It contains a built-in sample hold circuit. 6 types of conversion reference clocks can be switched by software. 14.1.1 Functions Table: 14.1.1 shows the A/D converter functions. Table:14.1.1 A/D Converter Functions AD0AD1AD2Page Interrupt cause AD0IRQ, AD0IRQB AD1IRQ, AD1IRQB AD2IRQ - Numbers of analog input pins Max. 6 pins Max. 8 pins Max. 10 pins - Resolution\ 10 bits - A/D converter clock selection IOCLK × 1

  • Panasonic MICROCOMPUTER MN103S, Chapter 13 Serial Interface 2 XIII - 32 Operation Table:13.3.14 Set value of Transfer Speed (Base Register value: hexadecimal) 1 8 32 128 1 8 32 128 1 8 32 128 1 8 32 128 300 C34 186 61 17 61A C2 30 B 186 30 B 2 61 B 2 - 960 3D0 79 1E 7 1E7 3C E 79 E 3 - 1E 3 - - 1200 30C 61 17 5 186 30 B 3 261B 2 - 172 - - 2400 186 30 B 2 C2 17 5 30 - - B - - - 4800 C2 17 5 - 61 B 2 17 9600 61 B 2 - 30 5 - B 19200 30 5 - - 17 28800 20 3 - F 38400 17 2 - B 76800 B IOCLK/n ( bps) 256 102432 64 Serial clock source timer underflow/n Timer clock source Transfer speed - - - - - 5 2 - - - - - - - - - - - - - - 5 3 2 - 5 2 - - - - - - - - - - - - - - - - - 5 2 - - - - - - - - - - - - - - - - - -

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