Apple CEC IIe Instruction Manual
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Apple CEC IIe, s t J i ri A; i !rF r'& Fa lr ,{$ ji tti 3| :,6 4 t,l 2? gi .ilFl g A 5 I 6 I F I s, lt Jr !l t D t-) i $. l" L ?r; tl Fl t a T B )t a -- 'Aj rg ti ^ih rl JHDI II "il I l!l tl fri $l t t F 6 fr * '5 A t ! v a.j !1. I a 'L : ?{ t? vo tt ft a I .+ a .l n ; |' a t q t' \t '!q !{ i{ ! .l ll I ,ir Fr$ ss st ;a t * 9ct ,6 tr I F rT u ! f <'t l' r$ s ra t11 T l{ d 'l i a a x r| a t ra t { a { 3 e t', $ii !! - !i i lrFts rt I a i"
Apple CEC IIe, $ 6. The Keyboard Connector (J17) Pin tlo. Name Description 4 r9 8 L2,L3, r0, 11r6,5,7 14 1s 16 +5v KSTRB RESET NC GND DATAO-DATA6 swo/oAPr -L2V swl /3APL Switch input, a input, normally -I2 volt power Switch input, input, normal Iy 1 2 +5V power supply. Strobe output from keyboard. This line should be given a pulse at least 10us long each time a key is pressed on the keyboard. THe strobe can be of either polarity, 6502's reset line. Normally'high; this line should be pulled low to restart the comp
Apple CEC IIe, Pin rro. Name Des cr ipt ion 25 +5V +5 VoIt power supply. 26 GND System common ground. , 27 DIVIA IN DITIA priority daisy-chain input. Usually connected to pin 24 (nUe OUT). 28 INT IN Interrupt priority daisy-chain input. Usually connected to pin 23 (rut rN). 29 NMI* Non-maskable interrupt to 6502. Pul 1 ing this line low starts an interrupt cycle. 30 IRq* Interrupt request Lo 6502. Pulling this line low starts an interrupt cycle only if the interrupt-disable (I) flag in the 6502 is not set. 31' RES* Pulling this line low initiates a reset routine. 32 . . INH*
Apple CEC IIe, III . CONNECTOR SPECIFICATION : I, The Auxiliary Slot (J0) Pin Assignment Pin no. Name Description I 3,58M 3. 58MHz video color reference signal. This line drives Z LS TTL loads . 2 VIDTM C1dcks the video dot out of ttre parallel-to-serial shift register. This line drives 2 LS TTL loads. Video horizontal and vertical sync signal. This line drives 2 LS TTL I oads . 3 SYNC* 4 ' PRAS * Mutipl exed RAI{ row-address strobe. This line drives 2 LS TTL loads. t 5 VC Third low-order vertical-counter
Apple CEC IIe, il , lr . fir .::;:1U $, DIAPI|II'JU S'T'., lii.:rl'dl-A tltl'.lr:i r Cr:\ (?;\.'7t--14 (:/L4i {3:ii:l*r.l-115 ]'Hr;H. iq$$. (.714 ) f;1.7::5*7i.i 1;:: F.lt/-iNlr. ilr:{:: I I (* l"lti'1"}.lE::$:t Fu/iFin f}r:ihiTls L Ili1" l F AHI" {+ I l- h: f'l $1-Y HS.*F't:S l--$-'tltlel' LS*r] l rl L$- 1::5 Lti- 1:.:;8 t_.1]-.1&*. t.-.ft*;l/.t.4 | (-'*.. r"t /l E::: f.- 1-, r:,. -1'r., t.-$*:;irii. l._. r._r ._., ./ -1' I t!.---.r rt | .' {.j$*'J. i..ii:;r (:]{l* l lirl I r:*.r:5$ I |:*'/41. .1. ra
Apple CEC IIe, ' Pln no. Name Description ' I cxxx Enables peripheral-card memory. 2 R/w245* Control data bus buffer. 3 RoMENI * Enables ROM #1. 4 EN80* Enables auxiliary RAM. 5 0 Ctock phase 0. 6 PRAS* Memory row-address strobe. 7 Q3 Timing signal. 8-10 RA7-RA5 Multiplexed address output. 11 cND Signal conmon. L2-I6 RA4-RA0 Multiplexed address output. 17 MD7 Data bus bit. 18-29 A0-A11 6502 address output. 30 VDD +5V system power. 31-34 A12-A15 65A2 ad
Apple CEC IIe, F--- r Addendurn ctcrtltt" corye to our attention that sone notherboarde are havlng a v:ldeo probleo. { ut ffi FF''i dt." 5, rrtno J1 uw "s _f- Alsre tOq CAr. drtgArrol l! ttq,,l*t?^ldtjil oqr.t ttcr.tq. io t j prl.l? Fot Tt*r t 6&qalrcr .6 ab[3 ?p+tttl 1; ?nr lt $fH* l. lK +Etl Jo hst6 JLt Pt* {t ce rJ9 ?*u Trf ts B[, rJq s cgc ] [e tdrfr{ ' hppt* ta lt d The followins changeD4g?, t\I4eLoor#rlftt,o1o;rec t these problens
Apple CEC IIe, F-F-t* F--- -F-- C---F---*----- Pin no. Name DescriPtion 37 47 50 52 53 54 55 56,57 58 59 60 CASEN* HO AN3 R/Yg't Q3 SEGB ENFIRM RA9*rRAl0* GR 7I.{ ENTl,lG* Column-address enable. This signal is disabled (heId high ) , during aciesses to memory on the auxiliary card, This line drives 2 LS TTL loads . Low-order horizontal byte This line drives 2 LS TTL Output of annunciator 3. drives 2 LS TTL loads. 6502 read/write signal . drives 2 LS TTL loads. 2MHz asymmetrical clock. drives 2 LS TTL loads. counter. loads. This line This line This line Second low-
Apple CEC IIe, - Pin no. Name Description 6 HO Display horizontal timing. 7-10 RA0-RA3 lvtultiplexed RAM address (phase 0). I I GND Signal common. t2-1 5 RA4-RA7 M"ltiplexed RAM address ( phase 0 ) . 16 0 lvlaster clock phase 0. L7 e3 Intermediate timing signal. 18 PRAS* Row-address strobe (phase 0). 19 A5 Address bit 6 from 6502. 20 coxx* r/O address enable. 2L SPKR Speaker output signal. 22 CASSO Cassette output signal. 23 R/W 6502 Read-Write control signal. 24 MD7
Apple CEC IIe, ;. R'M slor. ROM slot is a 16K ROM expansion card to install the dedicated operating program for the CEC IIe single board computers. Pin assignment as follows: Pin no. Name Description 1r15*24, N.C. 37-49r50 2-L 4 A0 -A12 No connection. Three state address lines from'6502. 25 +5V +5V power supply, 26 GND System ground.' 27-34 I4D7-MD0 Internal data bus. 3s ' 36 il3ilHil1:, Enab1e sisnals for the RoMs. 49 ROIIIOE* Enable signals for the ROM€ on the ROM card. IV. POWER REQUIREMENT. I To operate. .,the CEC IIe plus a full
Pin no Name Description 40 0 DEV1 * 41 42- 49 DO-D7 50 +L2v 3. Game I/O, Connector Signals. 6502 phase 0 clock. This line drives 2 LS TTL loads. Normal ly high i goes low during 0 when the 6502 addresses location $Conx, where n ig the slot number plus 8. This line drives 10 LS TTL Ioads. Three-state buffered bi-directional data bu
Apple CEC IIe, J15 Jg Signa I Pin no. Pin no. Name Description 15r14, 13r12 AN0-AN3 Annuciators. These lines are standard 7 4 LS TTL outputs. 9116 N.C. N?thing is connected to these plns . 4. Cassette T/o ( J9 , Jl 0 ) . J9 Phone jack is used as an input from the cassette recorder . J10 Phone jack is used as an output to the cassette recorder . The signal specification for cassette I/O are , , Input: I volt (nominal) from recorder Earphone or Monitor output, Input impedance is 12K ohms. Output z 25 .,millivolts to recoder Microphone input. Output impgdance is 100 ohms. .' 5. The Speaker
Apple CEC IIe, ?. The Inputr/Output Unit 6 5 3 01 6530L is designed with CMOS techonology; implements the following soft switches: ir Page 2 display (PAGE2), Hi-res mode (HIRES)' Text mode ( TEXT ) , Mixed mode (MIXED') , 80-column display ( B0 co1 ) , character-set select (ALTCHARSET ) any-key-down ' At'rnunciators , Vertica 1 bl anking ( VBL ) . The IOU generates the mulLiplexed address for the 64K dynamic RAIt'Is used in the CEC IIe for the data trarlsfers required for display and me
Apple CEC IIe, Pin rro. Name Description I 2 3 4 5 6 7 8 9 I6 L7 18 19 20 rO . GND 11 L2 14r{ HO 8 OVID* VIDT 3, 58I.{ CASEN* GR 7M SEGB ENTMG* PCAS * LDPS* 0 PRAS* VIDTM +5V l4 . 31 818 lvlHz master timing signal. Horizontal videos timing signal. Enab1e 8O-column disp}ay mode. Video data bit, 7 . 3. 57 9545 MHz timing signal . RAM enable. t Video display graphics-ffiod€ enable. 7 .L5909 MHz timing signal. Video timing signal. Power and signal cornmon. Enable master timing. j RAM .co lumn-address strobe . (fhis pin is not used
3 V. TROUBI.,E SHOOTING. During use of the CEC IIe single board computer should any trouble occur, do the following: 1. Make sure JP3 and JP4 short plugs are in position when t,he CEC IIe is in normal use. 2. Remove JP4 and press CONTROL RESET on keyboard to start self- test. If test fail s, contact the dealer for repair. 3. Whe
Apple CEC IIe, 3. The Memory Management Unit 65371 65371 is designed with CMOS technology, implements the fol lowing soft-switches : Page 2 display (PAGE2), Hi-res mode ( HrREs ) , store to 80- column card ( S0 STORE ) , select bank 2, enable bank-switched RAIvl, read auxiliary memory (RAMWRT ) , auxiliary stack and zero page (ar,rzpl , slot ROI'I for connector #3 (SLorC3Roll), slot ROIt'l in I/O space ( Sf-,OfCXROl*1) . The 65371 generates multiplexed address for memory reading and writing by the 6542 CPU. The 65371 pinouts: cxxx R/W245 * ROMEN1 * ENSO* 0 PRAS * Q3 RA7 RA5 RA5 GND RA4 RA3 RA2 RAl MD7
CEC IIe OPERATING INSTRUCTION I. Introduction. CEC IIe is an 8 bit personal computer using ROM SLOT (J21)' one 60 pin auxiliary'slot for 80 seven I/A slots for General Purpose peripheral computer's capability. a 6502 CPU with 64K Column Text Card'r and cards to extend the key and then press and release cold start instead of turning
Apple CEC IIe, Pin no. Name Description 25 26 24 27 28 29 CLRGAT* IovrD* ENSO* ALTVID* SEROUT* ENVID* +5V GND 14t4 PCAS * LDPS * Color-burst gating signal. This drives 2 LS TTL loads. Enables 8O-column display timing. This line drives'2 LS TTL loads. Enable for auxiliary RAM. This line drives 2 LS TTL loads Alternative video outPut to the video summing amplifier. Video serial output from parallel- to-serial shift register. Normally low; driving this line high disabl es the character generator such that the video dots from the shift register are all high
Apple CEC IIe, Pin no. Name Descript ion GROUND VIDEO -5V +l2v Power Connector (,rra, J20). J20 pin assignment: System common ground. NTSC-compatibl e po sitive video. white leve1 is volts, black level is vo1ts, and sync level is -5V power supply. +12V power supply. I 2 i L 1 composite about 2.0 about, 0.75 0 volts. 3 4 8. Pin no. Name Des cr ipt ion I 2 3 4 5 6 Ground +12V -5V -12v +5V +5V Common electrical ground. +12V from power supply. -5V .f rom power supply. -12V from power supply. + 5V f rom power suppl y .' +5V from power supply. J14 pin assignment: Pin no. Name Description I 2 3 4 5 6 Ground Ground +5V +L2Y - 12V -5V Common ele
Apple CEC IIe, R4-SH6 S.6H OHN L/4W (R??)'..r;,,,.r! R4*6t{.8 6.BH CIHl1 l/4W (R38fS1}rr...,'r R4*1?K l3l:: OHl"f r/4W (R36r58r5?f 44-46t 48) . t t | . .,.. r r.r r t R4-511t SIH OHPI L/4W (R4l)...trrt'rrrr R4*1ly,l0 1l"l oHl'l L/4ul (R47), ., r r r r r r r r ., "**__R?:e ln*f i oRn-17'fF*c-ffi*).-.*r, , ftd:-Ztn'7L lJnl-f a/{i;f!, \nr, r., t. r. | | r'.. ? RS-TKC' lH RES sIF 10 FIN q RES (RPS}. RS*3t(.5 S.,3H RES sIF 10 PIN (RPl ;?)... ?, EP*47$ 47 pF CAP. (C63)....rt.r..irrr I ' ;' cP-tot lrlrlrpF cAF. (c6
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