Alpha Data ADM-XRC-II Pro Hardware Manual

Text of Alpha Data ADM-XRC-II Pro User Guide:

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 25 of 29 Version 0.2 Pin Function UCF name Term Res VII Pro Pin Pin Function UCF name Term Res VII Pro Pin 1 Data[0] +ve User[0] R1 E10 2 Data[1] -ve User[2] R4 H13 3 Data[0] –ve User[1] - D10 4 Data[1] +-ve User[3] - G13 5 Data[2] +ve User[4] R3 E11 6 Data[3] +ve User[6] R2 D13 7 Data[2] –ve User[5] - F11 8 Data[3] -ve User[7] - C13 9 Data[4] +ve User[8] R5 H10 10 Data[5] +ve User[10] R6 L19 11 Data[4] –ve

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 14 of 29 Version 0.2 5.5 Flash Memory The XP supports a flash device connected to the V2PRO for general purpose applications. Typically in applications that use a PPC core the flash is used to hold bootstrap or application code. The flash memory has its own set of pins located within banks 3 and 4 of the V2Pro and the IO voltage on the Flash device is set at 2.5V. It is recommended that the LVCMOS_25 V2Pro IO standard be used for the Flash Interface. 2VP70 / 2VP100 FF1704

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 29 of 29 Version 0.2 Pin Function UCF name Tem Res VII Pro Pin Pin Function UCF name Tem Res VII Pro Pin 115 MGT_SYS_RXP22 N/a BB35 116 MGT_SYS_TXP22 N/a BB36 117 MGT_SYS_RXN22 N/a BB34 118 MGT_SYS_TXN22 N/a BB37 119 MGT_SYS_RXP11 N/a A3 120 MGT_SYS_TXP11 N/a A4 121 MGT_SYS_RXN11 N/a A2 122 MGT_SYS_TXN11 N/a A5 123 Single 5 R71 D19 124 Single 7 R69 F28 125 Single 4 - C19 126 Single 6 - E28 127 MGT_SYS_RXP10 N/a A7 128 MGT_SYS_TXP10 N/a A8 129 MGT_SYS_RXN10 N/a A6 130

• ADM-XP User Manual ADM-XR-IIPro User Manual Page 8 of 29 Version 0.2 The physical layout is shown in the diagram below. The DDR DRAM and DDR2 SSRAM devices are clam shelled and appear on both sides of the board. J5 - Jtag Header J 1 X R M M E Z Z J 2 J 4 JP1 - VIO Selection J 3 2V1500 Bridge 2VP70-2VP100 Target ZBT ZBT 1 Flash DDR DDR Flash M G T Power Clock Gen 11 1-2 3

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 11 of 29 Version 0.2 within the V2Pro device and the allocation of the MGT resources on the board the MGT’s are currently limited to 2.5GBps operation using the REFCLK input to the transceivers. The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200MHz, single ended. The local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by a divide by 2 in the ICS307. Although the clocks are related, phase is not guaranteed. A summary of the clock pin

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 5 of 29 Version 0.2 1 Introduction The ADM-XP (XP) is an advanced PCI Mezzanine card (PMC) supporting Xilinx Virtex-II PRO™ (V2PRO) devices, the latest development in FPGA technology. The XP supports 2VP70, 2VP100 or 2VP125 devices with two embedded PowerPC processors. The XP utilises an FPGA PCI bridge developed by Alpha Data supporting 64 bit PCI at up to 66MHz. Future enhancements will provide compatibility with PCI-X. A high speed mul

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 13 of 29 Version 0.2 5.4 DDR2 SSRAM The XP supports four independent banks of CIO DDR2 SSRAM memory. The devices fitted are Samsung 512K *36 (K7I163684-FC16) parts or a functional equivalent. As an upgrade option 1Mx36 (K7I323684-FC16) devices can also be fitted. 2VP70 / 2VP100 FF1704 Bank 6 VCCO=1.8V DDR2 SSRAM Add0[0:21] Dq0[0:31] DDR2 SSRAM Bank 0 Bank 7 VCCO=1.8V Bwe0[0:3] Cclk0/Cclkb0 Kclk0/Kclkb0 DDR2 SSRAM Add0[0:21] Dq0[0:31] Bwe0[0:3] Cclk0/Cclkb0 Kclk0/Kclkb0 DDR2 SSRAM Add1[0:21] Dq1[0:31] Bwe1[0:3] Cclk1/Cclkb1 Kclk1/Kclkb1 DDR2 SSRAM Add0[0:21] Dq0[0:31] Bwe0[0:3] Cclk0/Cclkb0 Kclk0/Kclkb0 DD

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 6 of 29 Version 0.2 2 Installation This chapter explains how to install the ADM-XP onto a PMC motherboard. 2.1 Motherboard requirements The XP is a 3.3V only PCI device and is not compatible with systems that use 5V signalling. The XP must be installed in a PMC motherboard that supplies 3.3V power to the PMC connectors. Ensure that the motherboard satisfies this requirement before powering it up. 2.2 Handling instructions Observe precautions for preventing damage to components by electrostatic discharge. Personnel handling the board should take SSD precautions. Avo

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 26 of 29 Version 0.2 Pin Function UCF name Tem Res VII Pro Pin Pin Function UCF name Tem Res VII Pro Pin 115 Data[48] +ve User[110] R65 C32 116 Data[49] +ve User[112] R61 K30 117 Data[48] -ve User[111] - C33 118 Data[49] -ve User[113] - J30 119 Data[50] +ve User[114] R68 H34(5) 120 Data[51] +ve User[116] R66 F24 121 Data[50] -ve User[115] - G34(5) 122 Data[51] -ve User[117] - E24 123 Data[52] +ve User[118] R71 D33 124 Data[53] +ve User[120] R69 L23 125 Data[52] -ve User[119] - E33 126 Data[53] -

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 20 of 29 Version 0.2 9 XRM-ETH 9.1 Introduction The XRM-ETH is a general-purpose adaptor for the ADM-XPL and ADM-XRC-II series of PMC modules. It provides 10/100 Ethernet, RS-232 and general purpose I/O for use with a wide variety of IP. The XRM-ETH is supplied with two cables to enable connections from the XRM-ETH to 15 way PC COM ports and RJ45 Ethernet. XRM-ETH-CAB01 for Ethernet XRM-ETH-CAB02 for RS232 IMPORTANT. The XRM-ETH REV 1 requires the use of 2.5V signalling over the XRM connector and this should be checked prior to power up. PHY PSU +3V3 +2V5 Filter Magnetics Infoport 15w TX

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 18 of 29 Version 0.2 7 User IO – PMC PN4 (rear panel) User I/O is presented on the User Connector Pn4 via a standard 64-way PMC connector. This should be routed via a suitable CMC compliant motherboard to an external I/O adapter. FPGA Pin Signal Pn4 Pin Pn4 Pin Signal FPGA Pin AY23 REARIO[1] 1 2 REARIO[0] AW23 AP23 REARIO[3] 3 4 REARIO[2] AR23 AN22 (gclk) REARIO[5] 5 6 REARIO[4] AP22(gclk) AW24 REARIO[7] 7 8 REARIO[6] AY24 AV24 REAR

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 21 of 29 Version 0.2 9.4 10/100 Ethernet The XRM-ETH Ethernet capability is supported by a Kendin KS8721B 2.5V PHY. This device is capable of auto-sensing 10 or 100Mb networks and has a standard MII interface suitable for connection to MAC IP in the FPGA. A management interface and reset is also provided. LEDS are provided on the board and these indicate the following conditions when lit. D1 Collision D2 Full Duplex D3 Speed is 100 D4

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 27 of 29 Version 0.2 11 User I/O XRM IO146 – Rocket The XRM-IO146 - Rocket is based on the XRM-IO146 module but has bank 4 on the mictor used to bring out the 7 MGT channels available on the ADM-XP boards. The termination scheme on the differential and single ended IO has also been changed from the standard XRM-IO146 allowing termination for LVPECL and BLVDS standards to be implemented on the XRM module rather than externally. FPGA IO CON Rs Rs Rs Rs Rt Rt User[0] User[1] User[2] User[3] The default manufacturing option is Rs=0R

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 22 of 29 Version 0.2 9.5 Input and Output Assignments (ADM-XP) 9.5.1 Mictor I/O FPGA XRM-ETH Bank Pin Samtec J2 Mictor Signal 1 E10 3 1 PAIR_1_P 1 D10 1 3 PAIR_1_N 1 D13 4 2 PAIR_2_P 1 C13 2 4 PAIR_2_N 1 E11 7 5 PAIR_3_P 1 F11 5 7 PAIR_3_N 1 H13 6 6 PAIR_4_P 1 G13 8 8 PAIR_4_N 1 H10 11 9 PAIR_5_P 1 J10 9 11 PAIR_5_N 1 L19 12 10 PAIR_6_P 1 M19 10 12 PAIR_6_N 1 F10 15 13 PAIR_7_P 1 G10 13 15 PAIR_7_N 1 K18 16 14 PAIR_8_P 1 L1

• Alpha Data ADM-XRC-II Pro, ADM-XR-IIPro User Manual Page 2 of 29 Version 0.2 Alpha Data 4 West Silvermills Lane Edinburgh EH3 5BD UK Phone: +44 (0) 131 558 2600 Fax: +44 (0) 131 558 2700 Email: [email protected] Alpha Data 226 Airport Parkway Suite 470 San Jose CA 95110 USA Phone: (408) 467 5076 Fax: (408) 436 5524 Email: [email protected] Copyright © 2002, 2003, 2004 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 4 of 29 Version 0.2 Contents 1 INTRODUCTION .......................................................................................................................................... 5 1.1 SPECIFICATIONS ...................................................................................................................................... 5 2 INSTALLATION ........................................................................................................................................... 6 2.1 MOTHERBOARD REQUIREMENTS ......................................................................................

• ADM-XP User Manual ADM-XR-IIPro User Manual Page 16 of 29 Version 0.2 (Continued) FPGA Pin Signal Connector Pins Signal FPGA Pin D20 IO_73N_1 61 62 IO_68N_1 H20 C20 IO_73P_1 63 64 IO_68P_1 J20 K17 IO_47N_1 65 66 IO_37N_1 F15 L17 IO_47P_1 67 68 IO_37P_1 E15 J17 IO_48N_1 69 70 IO_38N_1 C15 H17 IO_48P_1 71 72 IO_38P_1 C14 H18 IO_55N_

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 10 of 29 Version 0.2 5 Target FPGA The target FPGA is a V2PRO 2VP70, 2VP100 or 2VP125 (when available) in an FF1704 package. On the XP, all of the resources such as DDR, DDR2 SSRAM, IO and Flash are available no matter what device is fitted. The V2PRO has 8 banks of I/O and banks 0 and 1 provide the User IO to the front panel . The VCCIO voltage for banks 0 and 1 is selectable using JP1. JP1 Link Posn VCCIO – Front IO 1-2

• ADM-XP User Manual ADM-XR-IIPro User Manual Page 19 of 29 Version 0.2 8 JTAG Access The XP provides JTAG access for the fabric of the board through J6. This header will connect to Xilinx download cables using 3V3 signalling levels and has the following devices present in the scan chain :- hdr_TDI Bridge 2V1500 hdr_TMS hdr_TCK hdr_TDO Target 2VP70/ 2VP100 tck,tms The

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 15 of 29 Version 0.2 6 Front Panel I/O The XP supports standard XRM’s used on the ADM-XRC-II and ADM-XPL cards and also has an additional connector that brings 7 MGT channels upto the XRM Module site using a differential 28 pin Samtec QSE-DP series connector to maintain signal integrity. The XP supports the standard Samtec 180 pin connector but using either with 2.5V or 3.3V signalling which is globally selected using JP1 JP1 Link Posn VCCIO – Front IO 1-2 +3V3 2-3 +2V5 6.1 Samtec 180 connector - U8 The table

• ADM-XP User Manual ADM-XR-IIPro User Manual Page 17 of 29 Version 0.2 6.2 RocketIO Multi-Gigabit Transceivers – U13 The ADM-XP provides an additional connection upto the XRM module site which provides 7 MGT connection from the Virtex II pro device. This enables customisable Mulit Gigabit IO capability using XRM modules interfacing to the additional samtec QSE-DP connector

• Alpha Data ADM-XRC-II Pro, ADM-XP User Manual ADM-XR-IIPro User Manual Page 23 of 29 Version 0.2 9.5.3 Ethernet MAC All of these signals use VCCFPIO signalling levels. The VCCO selected by the jumper on the XRC-II/XPL should match the IOSTANDARD for these pins. FPGA XRM-ETH Bank Pin Samtec MAC Signal Comment 1 H20 62 RXC O-ST 1 G20 64 TXC O-ST 1 F15 66 PD I 1 E15 68 TXER I 1 C19 90 RXDV O-PD 0 G22 97 RXD3 O-PD 0 F22 99 RXD2 O-PD 1 D19 92 RXD1 O-PD 0 E28 94 RXD0 O-PD 0 F28 96 TXEN I 0 C29 98 TXD0 I 0 C28 100 TXD1 I 0 J22 102 TXD2 I 0 K22 104 TXD3 I 0 L27 106

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